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SECURITIES AND EXCHANGE COMMISSION
WASHINGTON, D.C. 20549
FORM 10-K
(MARK ONE)
[X] ANNUAL REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE
ACT OF 1934
For the fiscal year ended September 30, 1996
OR
[ ] TRANSITION REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES
EXCHANGE ACT OF 1934
For the transition period from to
Commission file number 0-45138
SYNOPSYS, INC.
(Exact name of registrant as specified in its charter)
Delaware 56-1546236
(State or other jurisdiction (I.R.S. Employer Identification Number)
of incorporation or organization)
700 East Middlefield Road
Mountain View, California 94043-4033
(Address of Principal Executive Offices, including ZIP Code)
Registrant's telephone number, including area code: (415) 962-5000
Securities registered pursuant to Section 12(b) of the Act:
Name of each exchange
Title of each class on which registered
None None
Securities registered pursuant to Section 12(g) of the Act: Common Stock, $.01
par value.
Indicate by check mark whether the Registrant (1) has filed all reports
required to be filed by Section 13 or 15(d) of the Securities Exchange Act of
1934 during the preceding 12 months (or for such shorter period that the
registrant was required to file such reports), and (2) has been subject to such
filing requirements for the past 90 days.
Yes X No
--- ---
Indicate by check mark if disclosure of delinquent filers pursuant to
Item 405 of Regulation S-K is not contained herein, and will not be contained,
to the best of registrant's knowledge, in definitive proxy or information
statements incorporated by reference in Part III of this Form 10-K or any
amendment to this Form 10-K. [ ]
The aggregate market value of voting stock held by nonaffiliates of the
Registrant as of November 29, 1996 was approximately $1,778,982,219.
On November 29, 1996, approximately 40,732,478 shares of the
Registrant's Common Stock, $.01 par value, were outstanding.
Documents Incorporated by Reference
(1) Portions of the Registrant's 1996 Annual Report to
Stockholders for the fiscal year ended September 30, 1996 are incorporated by
reference into Parts I, II and IV hereof.
(2) Portions of the Registrant's Notice of Annual Meeting and
Proxy Statement for the Registrant's Annual Meeting of Stockholders to be held
on February 28, 1997 are incorporated by reference into Part III hereof.
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Except for the historical information presented, the matters discussed in this
Form 10-K include forward-looking statements that involve risks and
uncertainties. The Company's actual results could differ materially from those
discussed herein. Factors that could cause or contribute to such differences
include, but are not limited to, those discussed under the caption "Factors That
May Affect Future Results" under "Management's Discussion and Analysis of
Financial Condition and Results of Operations" in the Company's 1996 Annual
Report to Stockholders, which is incorporated by reference in this Form 10-K.
* * * *
PART I
ITEM 1. BUSINESS
INTRODUCTION
Synopsys, Inc. (hereinafter sometimes referred to as the "Company")
develops, markets, and supports high-level design automation (HLDA) products for
designers of integrated circuits (ICs) and electronic systems. The Company
offers a range of design tools, verification systems and design reuse tools that
significantly improve designers' productivity by offering improved time to
market, reduced development and manufacturing costs, and enhanced design quality
of results when compared to earlier generations of electronic design automation
(EDA) products. The Company also provides training, support and consulting
services for its customers.
The foundation of the Company's HLDA methodology is logic synthesis.
The Company pioneered the commercial development of logic synthesis technology
in the late 1980s and is currently the leading provider of synthesis software.
The Company offers both logic and behavioral synthesis products. Logic synthesis
allows designers to use a high-level language to describe a chip, then
automatically converts and optimizes this high-level description into a
gate-level format that can be manufactured by a semiconductor company.
Behavioral synthesis allows designers to specify their designs at the behavioral
level, which is a higher level of abstraction than is permitted by logic
synthesis.
The Company's verification systems products are used by IC designers in
several stages of system design to help ensure that their ICs will work before
they are manufactured. The Company is a leading provider of software and
hardware models, which are used to test IC designs within the context of the
system into which they will be designed or to simulate the performance of an
entire system or subset of a system before manufacturing. The Company's
simulation products permit engineers to simulate their designs at various stages
of the design process (behavioral, register-transfer and gate-levels).
The Company's design reuse products are intended to reduce design time
by permitting the straight-forward reuse of previously-proven circuit "blocks."
The Company believes design reuse will be a key to increased productivity of IC
designers as the density and complexity of ICs increases. The Company's design
reuse products include its DesignWare(R) library of synthesizable standard parts
and its proprietary Cell-Based Array (CBA) IC architecture, libraries and
compilers, which are licensed to semiconductor manufacturers.
The Company markets its products on a worldwide basis and offers
comprehensive customer service, education, consulting, and support as integral
components of its product offerings. Products primarily are marketed through its
direct sales force. The Company has
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license agreements with many of the world's leading semiconductor, computer,
communications and electronics companies.
INDUSTRY BACKGROUND
EDA products have played a critical role in accelerating the dramatic
advances in the electronics industry over the past two decades.
For the past 26 years, IC complexity (as measured by the number of
transistors on a chip) has increased by a factor of 10 every six years - a
formula known in the semiconductor industry as Moore's Law (for the founder of
Intel Corporation). The need for EDA resulted from this increasing complexity,
as well as increased complexity of the electronic systems in which ICs are used
and the scarcity of skilled IC design engineers. Increased IC complexity
lengthened the product design and development cycles while, at the same time,
competition shortened product life cycles. The objectives of EDA are to (a)
reduce time to market, (b) reduce the costs associated with product design and
development, (c) improve the performance and density of complex IC designs, and
(d) improve the predictability of IC manufacture and testing.
The electronic design process encompasses five basic stages:
- Determine the architecture of the system (system design);
- Develop behavioral descriptions of various system elements
(behavioral design);
- Specify the desired architecture of an IC (functional design);
- Develop schematic diagrams of logic gates that implement this
functionality (logic or gate-level design); and
- Layout the individual transistors and interconnect wires that
implement the logic, which results in mask sets used to manufacture
the IC (layout or device design).
Prior to EDA, this entire process was manual, time consuming, prone to
error, and costly, thus limiting design complexity. In the 1960s and early
1970s, "complex" IC designs consisted of a few hundred logic gates (one logic
gate is equal to approximately four transistors). The EDA industry has evolved
over the past twenty years to automate a significant portion of the design
process, resulting in dramatic productivity increases. Each new generation of
design methods has been based on an enabling technology that provided an
automated linkage between design stages and raised the level of design
abstraction at which designers worked, thus facilitating the design of more
complex ICs by a broader range of designers.
The first generation of EDA, computer-aided design (CAD), automated the
layout process using dedicated mainframe or high-powered minicomputer systems,
allowing circuit designers to create ICs of several thousand logic gates. In the
late 1970s and early 1980s, computer-aided engineering (CAE) emerged as the
second generation of EDA, with electronic design capture at the logic gate-level
instead of the layout or device level. By the mid-1980s, most IC design was
accomplished using workstation-based CAE tools for schematic capture, gate-level
simulation, and automated placement and routing. In the late 1980s, as
semiconductor process technology advanced, it became possible to manufacture ICs
with hundreds of thousands of gates. Consequently, a new generation of EDA tools
was required that let designers work at even higher levels of abstraction.
The first successful step towards high-level design was the
introduction of hardware description languages (HDLs) that permitted the
expression of design ideas and functionality at a
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level independent of silicon implementation. Initial HDL modeling and system
simulation found only limited application because there was no enabling
technology that could translate the functional-level HDL specifications into
gate-level designs.
Logic synthesis provided the enabling technology that permitted
designers to translate HDL specifications into gate-level designs. Logic
synthesis employs a number of advanced computational algorithms for Boolean
logic manipulation and optimization, timing analysis, and technology mapping. By
raising the level of abstraction at which IC designers work from the gate-level
to the functional-level, logic synthesis has become the focal point of the third
generation of EDA.
Semiconductor process technology has continued to advance into the
1990s. Chip complexity and density have continued to increase accordingly. At
the same time, the competitive pressures faced by computer, telecommunications,
electronics, automotive and appliance companies and other designers and
consumers of ICs have made design productivity and time-to-market even more
critical factors in selecting IC design methods and tools.
STRATEGY
The Company's strategy is to lead the evolution of electronic design by
providing methodologies, products and services that maximize the productivity of
its customers. In order to execute this strategy, the Company seeks to develop a
balanced portfolio of design tools that continue to raise the level of
abstraction at which IC developers work and perform superior optimization of IC
design for speed, size and power, provide superior tools to assist in the
verification of IC designs early in the design cycle, enable the large-scale
reuse of intellectual property and provide high quality support, education and
consulting services that meet the needs of its customers.
PRODUCT GROUPS
Design Tools
Synopsys' design tools consist principally of its core synthesis
product, Design Compiler(TM), and a suite of high-level design products that are
tightly linked to it. The Company is currently the leading provider of logic
synthesis tools. Design Compiler was introduced in 1988 and has been updated
regularly. It is currently used by a broad range of companies engaged in the
design of ICs and field programmable gate arrays (FPGAs) to optimize their
designs for performance and chip area. In fiscal year 1996, the Company
introduced Power Compiler(TM), which permits IC designers to optimize their
designs for power consumption. Optimizing ICs for power consumption is
especially important for portable, battery-powered devices such as laptop
computers and cellular telephones.
In fiscal year 1996, the Company introduced FPGA Express(TM), a new
synthesis tool for high-density FPGAs and complex programmable logic devices
(CPLDs). FPGA Express is the Company's first product to run on the Windows 95
and Windows NT operating systems, reflecting the fact that personal computers
are the predominant platform for FPGA and CPLD designs.
The Company believes that behavioral synthesis is a key enabling
technology for the next advance in electronic design productivity. During fiscal
year 1996, Behavioral Compiler(TM), the Company's behavioral synthesis product,
continued to gain market acceptance. Behavioral synthesis permits engineers to
create complex circuits in a high-level shorthand; the designer specifies the
algorithm and the software then helps the designer pick the best architecture.
Early adopters of Behavioral Compiler (which was introduced in 1994) have
reported significant
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reductions in architecture design time (an important component of overall design
time), while achieving improvements in performance and area.
The Company's other design tools are integrated with Design Compiler to
offer a comprehensive design environment. HDL Advisor(TM) lets IC designers
analyze and improve their source code before synthesis and simulation runs. The
Company's test synthesis software permits designers to generate high-quality
test patterns and moves IC design testing from the final stages of the design
process to the high-level design process, thus permitting earlier detection of
design defects. The Company's power analysis product lets designers measure and
analyze power consumption earlier in the design cycle than layout-oriented tools
and Power Compiler automatically optimizes for power. The Company's
floorplanning management product acts as a high-level link to the layout process
by taking physical design data into consideration during synthesis.
Synopsys' design tools offer a number of benefits to customers. Its
synthesis products typically reduce circuit area up to 25% and improve
critical-path timing by approximately 30% when compared to the results achieved
by designers using traditional CAE tools. Logic synthesis supports technology
independent design, giving designers a wide array of options in choosing
semiconductor suppliers and, due to the automated nature of the process, allows
them to efficiently explore architectural alternatives by merely changing the
high-level description or reusing high-level descriptions from one design to
another. Synthesis also can be used to migrate designs from one technology to
another (e.g., CMOS 0.5-micron to CMOS 0.25-micron technology) or retarget from
one implementation approach to another (e.g., FPGA to ASIC (application specific
IC)).
In order to address the challenges posed by increasing IC complexity
and advances in IC technology, in fiscal year 1996 Synopsys formed a number of
important strategic relationships. In February 1996, the Company and
International Business Machines Corporation (IBM) formed an alliance to jointly
develop products in the areas of design planning, timing, test and synthesis,
and the Company acquired a license to use certain IBM technology. In addition,
the Company was selected by SEMATECH, a consortium of the leading U.S.
semiconductor manufacturers, as the prime contractor on a $6 million contract to
deliver next generation tools for designing complex ICs at 0.25-micron and
below. In May 1996, the Company entered into a strategic relationship with
Cooper & Chyan Technology (CCT), Inc. to link the Company's synthesis tools with
CCT's routing technologies. CCT recently announced an agreement to merge with
Cadence Design Systems, Inc., a competitor of the Company. Synopsys is currently
evaluating its relationship with CCT in light of the proposed merger.
Verification Systems
Verification is the process of ensuring that an IC meets the functional
specifications and timing requirements of its design, and that it will work with
the other components of a system, before it is manufactured. As IC complexity
grows, the importance of verification to the chip design process also grows.
Without adequate verification tools, verification can be a serious bottleneck in
the design process.
The Company offers a range of verification products, including
simulation and emulation tools and hardware and software models, integrated into
its synthesis-based design flow, that help customers verify their designs before
committing them to silicon.
In September 1996, the Company introduced two new products that help
address the verification demands of designing increasingly complex ICs.
Cyclone(TM), the Company's new "cycle-based" simulation software, permits IC
designers to simulate their designs using high-level algorithms at the
register-transfer level, which is faster and requires less memory than
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current tools. Synopsys' ARKOS(TM) hardware emulator emulates the behavior of an
ASIC with up to 4 million gates and can operate as an execution engine for
Cyclone, providing accelerated simulation. Together, Cyclone and the ARKOS
hardware emulator permit designers to use emulation and simulation early in the
design process.
Cyclone and the ARKOS hardware emulator complement the Company's VHDL
System Simulator(TM) (VSS). VSS is used at various stages in the high-level
design process to simulate a system or subsystem to simulate the performance of
an IC within a system. During fiscal 1996, the Company added VSS support for
"VITAL," the industry signoff gate-level modeling standard. VSS, Cyclone and the
ARKOS emulator are all tightly linked to the Company's synthesis products.
Since the Company's February 1994 merger with Logic Modeling
Corporation, the Company has offered a full range of hardware and software
modeling solutions. The Company currently offers models for more than 13,000
commercially available ICs, including a wide range of microprocessors, DSPs,
CPLDs, memories and standard logic. In addition, the Company offers modeling
technologies to allow designers to create models of both standard and
proprietary devices. These models support all major EDA simulation environments
and a wide range of EDA platforms, giving designers access to a broad range of
models to assist them with verification of their designs.
Success in the modeling business depends, in part, upon making a wide
range of models and model types. The Company continues to focus its modeling
development efforts on enhancing its ability to quickly and efficiently produce
and distribute new models. The Company seeks to maintain close relationships
with leading semiconductor vendors to ensure model accuracy and the earliest
possible availability. The Company believes that future design verification
methodologies will require models of even more complex components, subsystems,
and systems as customers engage in ever larger and more sophisticated designs.
Design Reuse
As the number of logic gates on ICs continues to grow, and as ICs
themselves become capable of hosting entire systems rather than single
functions, the reuse of proven design modules will become increasingly important
to IC designers. The Company's design reuse products are intended to enable such
reuse.
Since the Company's acquisition of Silicon Architects(TM) in May 1995,
it has offered a proprietary IC architecture, known as Cell-Based Array (CBA),
and compilers for high-level memories and data path elements. The CBA
architecture consists of optimized libraries of low level elements in an IC. The
Company licenses these libraries to ASIC manufacturers and adapts the libraries
for use in the manufacturer's particular production process. The CBA libraries
are then used in lieu of the manufacturer's proprietary library. Replacing
vendor-specific libraries with optimized CBA libraries can provide cost benefits
to ASIC vendors by reducing the silicon area required for a given design and can
provide improved performance and power consumption levels compared to other IC
architectures. The CBA architecture also offers the Company's customers a link
between synthesis-based high-level design and the physical implementation of
designs. The Company has entered into CBA license agreements with many of the
world's leading ASIC vendors.
DesignWare, introduced in 1992, provides IC designers with libraries of
pre-designed and pre-verified off-the-shelf design modules to incorporate into
their own designs. By providing these building blocks and making them
synthesizable (i.e., usable by the Company's design tools in optimizing a
design), DesignWare helps reduce the overall design time for complex ICs. The
reuse of these building blocks represents a significant shift from traditional
IC
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design, in which designs have been intimately tied to a particular process
technology or design methodology and not easily transferred from one chip design
to the next. By the end of fiscal year 1996, over 100 design modules were
available in DesignWare libraries. The Company intends to make more modules
available and to increase the size and functions of the available modules.
DesignWare Developer(TM) is used in conjunction with DesignWare and permits
designers to create their own proprietary reusable DesignWare components.
PRODUCTS
The Company's products include design tools, verification systems and
design reuse tools, as summarized below. In addition, the Company offers
interface products that permit the sharing of data with other EDA systems and
library tools that assist semiconductor vendors in developing technology
libraries.
Design Tools
Behavioral Compiler. Behavioral Compiler provides a direct link from
the functional descriptions of a design to HDL Compiler(TM) and Design Compiler
for implementation. By permitting IC designers to work at a higher level of
abstraction than permitted by other tools, Behavioral Compiler simplifies IC
design and, in the process, makes the design more reliable and predictable.
HDL Compiler Family. The HDL Compiler family includes VHDL Compiler and
HDL Compiler (for Verilog). The HDL Compiler family synthesizes HDL descriptions
into optimized, technology independent netlists for the Design Compiler family.
Design Compiler Family. The Design Compiler family consists of products
that synthesize hierarchical descriptions of circuits in any combination of
equations, state tables, and netlists from external CAE systems or the Synopsys
HDL Compiler family and optimizes such designs to meet timing and area
requirements given a particular technology library.
Power Family. Includes DesignPower(R) and Power Compiler, offering a
complete methodology for power. DesignPower analyzes power consumption early in
the design process, helping to avoid surprises late in the design process that
could force designers to use more expensive packaging, "re-spin" designs, and/or
add cooling devices to meet power consumption requirements. Power Compiler
offers "push button" power optimization on top of designs developed with
DesignPower. When used in conjunction with Design Compiler, Power Compiler
enables simultaneous optimization for size, timing and power.
FPGA Compiler(TM). FPGA Compiler works with the Design Compiler to
synthesize designs for implementation in Field Programmable Gate Arrays (FPGAs)
from a number of manufacturers, including Actel, Altera, Lucent Technologies and
Xilinx.
FPGA Express. FPGA Express offers synthesis and optimization for FPGAs
and complex programmable logic devices on Windows 95 or Windows NT-based PCs.
Test Compiler(TM). Test Compiler works with the Design Compiler family
to integrate testability analysis and design-for-test capabilities into the
design process. Test Compiler lets designers explore testability trade-offs
early in the design process and automatically generates vectors needed to test
the design.
HDL Advisor. HDL Advisor helps designers reduce the number of design
iterations by providing a source-level performance analysis tool for use either
before or after synthesis or simulation.
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DesignTime(TM). DesignTime delivers full static timing analysis within
Synopsys' high-level design environment, permitting a designer to perform
point-to-point timing analysis using the same vendor-certified libraries, timing
algorithms, and interfaces used to create the design.
Floorplan Manager(TM). Floorplan Manager takes into account physical
design information from a commercial floorplanner early in the design process,
promoting convergence between synthesis and layout and reducing design time by
reducing post-layout timing violations.
COSSAP. COSSAP(R) is a second-generation DSP design system that can
simulate large, complex, high-level systems that would be hard to model with
standard cycle-based or event-driven simulators. COSSAP includes a library of
DSP building blocks.
Verification Systems
VHDL System Simulator (VSS) Family. The VSS family provides a single
simulation environment for the three major stages of IC design -- behavioral,
logic, and gate -- letting designers capture and verify high-level
specifications and detect design inconsistencies before and after committing
designs to synthesis. It also includes a source-level debugging tool and
post-processing utilities, including statistical analysis.
Cyclone. Cyclone, the Company's new "cycle-based" simulation software,
permits IC designers to simulate their designs using cycle-based algorithms at
the register-transfer level, which is faster and requires less memory than
current tools.
ARKOS Emulator. Synopsys' ARKOS hardware emulator emulates the behavior
of an ASIC with up to 4 million gates and can operate as an execution engine for
Cyclone, providing accelerated simulation.
ModelSource(TM) 3000 Hardware Modeling Products. The ModelSource 3000
series is a family of hardware modeling systems for ASIC and board level design
which provide a flexible means for designers to model complex devices.
ModelSource 3000 systems use the actual integrated circuit to model its own
behavior.
SmartModel(R) Library and SourceModel Library(R). These two libraries
include models of more than 13,500 devices, representing all major device types
and semiconductor manufacturers. The SmartModel Library features models of
complex devices--microprocessors, controllers, peripherals, FPGAs and logic
devices--that engineers would not typically model themselves. The SourceModel
Library offers designers models of commonly-used standard logic and memory
devices. Models are furnished in either Verilog or VHDL source code.
Bus Interface Models. Bus interface models are used to verify that
designs comply with established industry standards. Models are available for
popular standards including: Peripheral Component Interface (PCI), Personal
Computer Memory Card International Association (PCMCIA), MicroChannel
Architecture (MCA), Industry Standard Interface (ISA), Extended Industry
Standard Interface (EISA), Small Computer Systems Interface-2 (SCSI-2), and
Versa Module Eurocard (VME) standards.
Telecommunications Workbenches. The Company's Telecommunications
Workbench products provide a high-level design verification environment for
telecommunications applications.
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Design Reuse
DesignWare. DesignWare provides libraries of flexible, ready-to-use
digital components that are technology-independent, parameterizable and
synthesizable. DesignWare libraries include commonly used functions ranging from
simple modules, such as multipliers, to more complex functions. DesignWare
libraries are tightly coupled to the Company's high-level design environment.
DesignWare Developer(TM). DesignWare Developer helps customers develop
their own DesignWare components from which they can build an inventory of design
knowledge that can be leveraged across multiple development teams or in
subsequent design cycles.
Cell-Based Array (CBA) Architecture and Macrocell Libraries. The
Company's CBA architecture offers semiconductor vendors the customization
advantages of gate array architecture with the density and performance and power
advantages of standard cell design. Macrocell libraries contain circuit elements
used by the CBA Design System(TM) and Synopsys synthesis tools. Compilers for
complex datapath and memory blocks based on CBA are also available.
Memory and Datapath Compilers. Compilers are used to quickly generate
optimized general purpose functions for an IC, and are parameterized to allow
the designer to generate a function of optimal size, performance and power.
CBA Design System. The CBA Design System provides several Silicon
Architect-developed tools with integration of commercial EDA tools to facilitate
design of complex ICs based on the CBA Architecture.
CUSTOMER SERVICE AND SUPPORT
The Company devotes substantial resources to providing customers with
technical support, customer education, and consulting services. The Company
believes that a high level of customer service and support is critical to the
adoption and successful utilization of its high-level design automation
methodology.
As a result of the continued growth of the Company's installed base, as
well as customer requests for education, support and consulting services, the
Company's service revenue has increased as a percentage of total revenue,
representing 31%, 32% and 34% of total revenue in fiscal 1994, 1995, and 1996,
respectively.
Technical Support
Technical support is provided through both field- and corporate-based
technical application engineering groups. The Company provides customers with
software updates and a formal problem identification and resolution process
through the Synopsys Technical Support Center. The Company's central entry point
of all customer inquiries is SOLV-IT!(R), a direct-access service available
worldwide, 24 hours per day, through electronic mail and the World Wide Web that
lets customers quickly seek answers to design questions or more insight into
design problems. SOLV-IT! combines Synopsys' complete design knowledge database
with sophisticated information retrieval technology. Updated daily, it includes
documentation, design tips, and answers to user questions.
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Customer Education Services
Synopsys offers a number of workshops focused on high-level design,
simulation, behavioral synthesis, logic synthesis, and test. Regularly scheduled
workshops are offered in Mountain View, California; Austin, Texas; Burlington,
Massachusetts; Reading, England; Rungis, France; Munich, Germany; Tokyo and
Osaka, Japan; and Seoul, Korea. On-site workshops are available on a worldwide
basis at customers' facilities. To date, over 15,000 design engineers have been
trained in the use of Synopsys' products through participation in Company
workshops.
Consulting
The Company provides consulting services through its Professional
Services Group, which offers customized high-level design support for IC and
systems designs. Synopsys consultants are experienced designers who provide
customers with in-depth technical expertise in the use of Synopsys' HLDA
methodology and tools. Synopsys offers both methodology and project consulting.
Methodology consulting is aimed at increasing customer productivity, promoting
the adoption of the Company's HLDA methodology and solving immediate needs of
customers' design teams. Project consulting involves Synopsys experts working
with customer design teams from design implementation through simulation,
synthesis and tapeout.
PRODUCT WARRANTIES
The Company generally warrants its products to be free from defects in
media and to substantially conform to material specifications for a period of 90
days. The Company has not experienced significant returns to date.
SUPPORT FOR INDUSTRY STANDARDS
The Company actively supports standards that it believes will help its
customers increase productivity and solve design problems, including support for
key standards that promote system-on-chip design and allow tool
interoperability. The Company's products support the two most commonly used
hardware description languages, VHDL and Verilog HDL. The Company's de facto
standard register-transfer-level subsets of the VHDL and Verilog languages were
donated to the EDA Industry Council for its project to create a formal standard
RTL subset. Netlist and schematic input/output are supported through the
Electronic Data Interchange Format. The products support simulation modeling
with the VHDL Initiative Towards ASIC Libraries (VITAL) standard. Ties to
physical design tools are provided by the Company's support of Standard Delay
Format and Physical Design Exchange Format. The latter was donated to the
industry for standardization as part of a Delay Calculation System for deep
submicron design. The Company contributes to this Delay Calculation System
standardization effort which includes, in addition to PDEF, the Delay
Calculation Language (DCL), donated by International Business Machines
Corporation, and the Standard Parasitic Extended Format, donated by Cadence
Design Systems, Inc. The Company donated its SWIFT modeling interface to the
Open Modeling Forum for a common simulator interface from models written in
various formats.
The Company is on the Board of Directors of the standards groups Open
Verilog International, VHDL International, Open Modeling Forum (OMF), and CAD
Framework Initiative. As a member of SEMI/SEMATECH and the EDA Industry Council,
the Company is participating in the EDA Industry Standards Roadmap and the
active projects that are implementing the Roadmap. The Company is the prime
contractor for SEMATECH's Chip Hierarchical Design System, which is predicated
on open standards. The Company also contributes to the efforts of the Design
Automation Standards Committee of the IEEE. The
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Company's software is chiefly written in C language and utilizes the Motif and
X11 standards for graphical user interfaces. The Company's software runs
principally under the UNIX operating system and is offered on the most widely
used workstation platforms, including those from Sun Microsystems,
Hewlett-Packard, IBM, Digital Equipment Corporation and Sony. Certain of the
Company's software modeling products and FPGA Express run on the Windows '95 and
Windows NT operating system and are available for IBM-compatible PCs.
SALES, DISTRIBUTION AND BACKLOG
The Company markets its products and services primarily through its
direct sales and service force in over 30 offices in the United States and
principal international markets. The Company employs highly skilled engineers
and technically proficient sales persons capable of serving the sophisticated
needs of the customers' engineering and management staffs.
For fiscal 1994, 1995, and 1996, international sales represented 48%,
52%, and 49%, respectively, of the Company's total revenue. Additional
information relating to domestic and foreign operations is contained in Note 8
of Note to Consolidated Financial Statements on page 42 of the Company's 1996
Annual Report to Stockholders.
As of September 30, 1996, the Company's direct sales and service force
consisted of 600 management, technical, and administrative employees. The
Company has nineteen sales/support centers throughout the United States.
Internationally, the Company has sales/support offices in Canada, Finland,
France, Germany, Hong Kong, Israel, Italy, Japan, Korea, the People's Republic
of China, Singapore, Sweden, Taiwan, and the United Kingdom, including regional
headquarters offices in Germany, Japan and Singapore. On a limited basis, the
Company also utilizes manufacturer's representatives and distributors. The
Company has established such relationships in Australia, Brazil, Hong Kong,
India, Korea, Malaysia and Singapore.
The Company's backlog was approximately $176.4 million on November 2,
1996, as compared to $99.4 million on November 4, 1995. The Company's backlog
includes orders for customer training and consulting services which are expected
to be completed within one year, orders for systems and software products and
related maintenance and support with customer requested ship dates within three
months, and deferred revenue, which consists of subscription services,
maintenance and support. The Company has not historically experienced
significant cancellations of orders. Customers frequently reschedule or revise
the requested ship date of orders, however, which can have the effect of
deferring recognition of revenue for these orders beyond the expected time
period.
RESEARCH AND DEVELOPMENT
The Company believes that its future performance will depend in large
part on its ability to maintain and enhance its current product lines, develop
new products, maintain technological competitiveness, and meet an expanding
range of customer requirements. In addition to product development teams, the
Company maintains an advanced research group that is responsible for exploring
new directions and applications of the core technologies, migrating new
technologies into the existing product lines, and maintaining strong research
relationships outside the Company both within industry and academia.
Relationships are maintained with third-party software and hardware vendors to
broaden the product lines without direct investment and with all major hardware
vendors on whose platforms the Company's products operate.
During fiscal 1994, 1995, and 1996, research and development expenses
were $41.3 million, $58.7 million, and $84.2 million, respectively, excluding
capitalized software development costs. Capitalized software development costs
for these periods were $1.5 million,
11
<PAGE> 12
$1.0 million, and $1.0 million, respectively. The Company anticipates that it
will continue to commit substantial resources to research and development in the
future.
MANUFACTURING
The Company's manufacturing operations consist of assembling, testing,
packaging and shipping its hardware and software products and documentation
needed to fulfill each order. All manufacturing is currently performed in the
Company's Mountain View, California and Beaverton, Oregon, facilities. Outside
vendors provide tape and CD-ROM duplication, printing of documentation and
manufacturing of packaging materials. The manufacturing and test of hardware
products is done by Company employees, with some sub-assembly performed by
outside vendors. The Company typically ships its software products, with either
a permanent or temporary access key, within 10 days of acceptance of customer
purchase orders and execution of software license agreements, unless the
customer has requested otherwise. For its hardware products, the Company buys
components in anticipation of orders and builds units to match orders, typically
shipping within four to twelve weeks of order acceptance, unless the customer
has requested otherwise.
COMPETITION
The EDA industry is highly competitive. The other principal companies
in the EDA industry are Cadence Design Systems, Inc., Mentor Graphics Corp.,
Viewlogic Corporation, Avant! Corporation and Quickturn Design Systems Inc.
There are many other companies in the EDA industry and frequent new entrants,
including businesses targeted at Synopsys' product areas.
The Company's products compete with similar products from other
vendors and compete with other EDA products and services for a share of the EDA
budgets of their customers. The Company believes that the principal competitive
factors in the EDA market are product performance, technology leadership,
methodology support, technical support, support of industry standards, price,
and reputation. The Company believes that it currently competes favorably with
respect to these factors.
To date, the majority of the Company's revenue has resulted from sales
of synthesis and synthesis-related HLDA tools, and modeling products, both
market segments in which the Company is currently the leading provider. As the
Company's business evolves, it expects to continue to face competition in the
core product areas of synthesis and modeling and to face competition both in new
product areas and from competing alternatives for its customers' EDA dollars
(e.g., internal spending, services, out-sourcing of design or other tools).
Although the Company has maintained its market leadership in synthesis and
modeling, a loss of market share or price/margin reduction resulting from
increased competition could have a significant adverse effect on the Company.
More generally, the EDA industry as a whole is experiencing rapid
change. Technology advances and market requirements are fueling a change in the
nature of competition among EDA vendors. Advances in semiconductor technology
are expected to create a need for tighter integration between logic design and
physical design, and companies will increasingly compete over "design flows"
involving a broad range of products and services rather than individual design
tools.
No single EDA company currently offers its customers industry leading
products for a complete design flow. Presently, the Company does not offer
physical design tools, a market which is currently dominated by Cadence and
Avant!, and trails Cadence in its capacity to offer design services. In May
1996, the Company entered into a strategic relationship with Cooper &
12
<PAGE> 13
Chyan Technology, Inc. (CCT) to link the Company's existing synthesis products
and its design planning products under development with CCT's routing
technology. Cadence and CCT have announced their intention to merge. The Company
is evaluating the effect of such a merger on its relationship with CCT.
To counter competition, the Company will continue to enhance its
product line and promote the adoption of new products and methodologies.
However, there can be no assurance that the Company will be able to compete
successfully against current and future competitors or that competitive pressure
faced by the Company will not materially adversely affect its business,
operating results and financial condition.
PRODUCT SALES AND LICENSING AGREEMENTS
The Company offers its hardware products for sale or lease. The Company
typically licenses its software to customers under non-exclusive license
agreements that transfer title to the media only and that restrict use of the
software to internal purposes at specified sites. The Company currently licenses
the majority of its software as a network license that allows a number of
individual users to access the software on a defined network. License fees are
dependent on the type of license, product mix and number of copies of each
product required. On certain software products the Company will collect royalty
payments in addition to license fees.
PROPRIETARY RIGHTS
The Company primarily relies upon a combination of copyright, patent,
trademark and trade secret laws and license and nondisclosure agreements to
establish and protect proprietary rights in its products. The source code for
the Company's products is protected both as a trade secret and as an unpublished
copyrighted work. However, it may be possible for third parties to develop
similar technology independently, provided they have not violated any
contractual agreements or intellectual property laws. In addition, effective
copyright and trade secret protection may be unavailable or limited in certain
foreign countries. Because the EDA industry is characterized by rapid
technological change, the Company believes that factors such as the
technological and creative skills of its personnel, new product developments,
frequent product enhancements, name recognition and reliable product
maintenance, coupled with the various forms of legal protection that are
available for its technology, provide an effective means for the Company to
establish and maintain a technology leadership position. The Company currently
holds several U.S. and foreign patents on some of the technologies included in
its products and will continue to pursue additional patents in the future.
Although the Company believes that its products, trademarks and other
proprietary rights do not infringe on the proprietary rights of third parties,
and although to date the Company has received no communications from third
parties alleging the infringement of the proprietary rights of such parties,
there can be no assurance that infringement claims will not be asserted against
the Company in the future or that any such claims will not require the Company
to enter into royalty arrangements or result in costly and time-consuming
litigation.
EMPLOYEES
As of September 30, 1996, the Company had a total of 1,716 employees,
of whom 1,333 were based in the United States and 383 were based
internationally. Of the total, 762 were engaged in marketing, sales and related
customer support services, 548 were in research and development, 123 were in
operations and 283 were in administration and finance. The Company's future
financial results depend, in part, upon the continued service of its key
technical and senior management personnel and its continuing ability to attract
and retain highly qualified
13
<PAGE> 14
technical and managerial personnel. Competition for such personnel is intense
and there can be no assurance that the Company can retain its key managerial and
technical employees or that it can attract, assimilate or retain other highly
qualified technical and managerial personnel in the future. None of the
Company's employees is represented by a labor union. The Company has not
experienced any work stoppages and considers its relations with its employees to
be good.
ITEM 2. PROPERTIES
The Company's principal administrative, sales, marketing, research and
development facilities are located in five adjacent buildings in Mountain View,
California, which together provide approximately 415,000 square feet of
available space. These buildings are leased through February 28, 2003.
On January 2, 1996 the Company entered into a build-to-suit lease
arrangement for two buildings in Sunnyvale, California, within one-half mile
from its principal offices. The buildings will provide approximately 200,000
square feet of additional space, and are expected to be available for occupancy
in mid-1997. The lease term is ten years from the date of occupancy.
The Company leases approximately 53,000 square feet in Beaverton,
Oregon for administrative, marketing, research and development and support
activities. This facility is leased through December 31, 1998.
The Company currently leases nineteen other domestic sales offices
throughout the United States. The Company currently leases international sales
and/or service offices in Canada, Finland, France, Germany, Hong Kong, Israel,
Italy, Japan, Korea, the People's Republic of China, Singapore, Sweden, Taiwan,
and the United Kingdom. The Company also leases a research and development
facility in India.
The Company believes that its existing facilities are adequate for its
current needs and that additional space will be available as needed.
ITEM 3. LEGAL PROCEEDINGS
There are no material legal proceedings pending against the Company.
ITEM 4. SUBMISSION OF MATTERS TO A VOTE OF SECURITY HOLDERS
No matters were submitted for a vote of security holders during the
fourth quarter of the fiscal year covered by this Report.
Executive Officers of the Company
The executive officers of the Company and their ages, as of December 20, 1996,
are as follows:
Name Age Position
Harvey C. Jones, Jr. 43 Chairman of the Board of Directors
Aart J. de Geus 42 President, Chief Executive Officer and
Director
14
<PAGE> 15
Chi-Foon Chan 47 Executive Vice President, Office of the
President, Senior Vice President, Design
Tools Group and Design Reuse Group
William W. Lattin 56 Executive Vice President and Director
David C. Bullis 44 Senior Vice President, Verification
Systems Group
Sally A. DeStefano 49 Senior Vice President, Human Resources
and Facilities
Alain J. Labat 41 Senior Vice President, Worldwide Field
Operations
Paul Lippe 38 Senior Vice President, Business
Development & Legal, Secretary
A. Brooke Seawell 49 Senior Vice President, Finance and
Operations, and Chief Financial Officer
Harvey C. Jones, Jr. joined the Company in December 1987 and has been
serving as Chairman of the Board since December 1992. He was first elected as a
Director in 1988. He served as Chief Executive Officer from December 1987 until
January 1994. Prior to joining Synopsys, Mr. Jones served as President and Chief
Executive Officer of Daisy Systems Corporation, a CAE company he co-founded in
1981. From 1974 to 1981, Mr. Jones was employed by Calma Company, a CAD company,
where his last position was Vice President, Business Development. Mr. Jones
holds a B.S. in mathematics and computer sciences from Georgetown University,
and an M.S. in management from the Massachusetts Institute of Technology. Mr.
Jones is a director of Remedy Corporation, a developer of client/server
software.
Dr. Aart J. de Geus co-founded the Company in December 1986 and
currently serves as President and Chief Executive Officer. He has served as a
Director since 1986. He served as President from December 1992 until January
1994. Prior to December 1992, Dr. de Geus served as Chairman of the Board and
Senior Vice President, Marketing of the Company. Prior to his appointment as
Senior Vice President, Marketing, Dr. de Geus served as the Company's Senior
Vice President, Engineering. From 1982 to 1986, Dr. de Geus was employed by
General Electric Corporation, where he was the Manager of the Advanced
Computer-Aided Engineering Group. Dr. de Geus holds an M.S.E.E. from the Swiss
Federal Institute of Technology in Lausanne, Switzerland, and a Ph.D. in
electrical engineering from Southern Methodist University.
Dr. Chi-Foon Chan joined the Company in May 1990 and currently serves
as Executive Vice President, Office of the President. He also serves as Senior
Vice President, Design Tools Group (since February 1994) and Design Reuse Group
(since October 1996). Prior to February 1994, Dr. Chan served as Vice President,
Engineering and General Manager, DesignWare Operations, and prior to October
1993, he served as Vice President, Application Engineering and Services. From
March 1987 to May 1990, Dr. Chan was employed by NEC Electronics, a diversified
electronics company, where his last position was General Manager of the
Microprocessor Division. Dr. Chan holds an M.S. and a Ph.D. in computer
engineering from Case Western Reserve University.
15
<PAGE> 16
Dr. William W. Lattin is an Executive Vice President of the Company and
has been a Director of the Company since July 1995. Dr. Lattin joined the
Company in February 1994 in connection with the Company's merger with Logic
Modeling Corporation ("LMC"). From October 1994 to July 1995 he served as the
Company's Senior Vice President, Corporate Marketing, and from February 1994
until October 1994 Dr. Lattin served as Senior Vice President, Logic Modeling
Group. From December 1992 to February 1994, Dr. Lattin served as President,
Chief Executive Officer and Director of LMC, and from May 1992 to December 1992
he served as Chairman of the Board and Chief Executive Officer of LMC. From 1986
to May 1992, Dr. Lattin served as Chairman of the Board of Directors, President
and Chief Executive Officer of Logic Automation Incorporated, a predecessor of
LMC. Dr. Lattin holds a B.S.E.E. and an M.S.E.E. from the University of
California at Berkeley, and a Ph.D. in Electrical Engineering from Arizona
State.
David C. Bullis joined the Company in February 1994 in conjunction with
the merger of Synopsys and LMC, and currently serves as Senior Vice President,
Verification Systems Group. Prior to October 1994, Mr. Bullis served as Vice
President, SmartModel Division. From May 1993 to February 1994, Mr. Bullis
served as Vice President and General Manager, SmartModel Division of LMC and
from May 1992 to May 1993, he served as Vice President, Sales of LMC. From 1991
to May 1992, Mr. Bullis served as Vice President, Sales of Logic Automation
Incorporated. From 1984 to 1991, Mr. Bullis was employed by Summation Inc., a
manufacturer of systems for board testing, most recently as Chief Executive
Officer. Mr. Bullis holds a B.S.E.E. from Iowa State University and an M.S.E.E.
from Colorado State University.
Sally DeStefano joined the Company in June 1995 and currently serves as
Senior Vice President, Human Resources and Facilities. From June 1989 until June
1995, Ms. DeStefano was Vice President of Human Resources of Sybase, Inc., a
vendor of client/server software and services for building enterprise-wide
information systems. From April 1986 to May 1989, Ms. DeStefano served as
Director, then Vice President of Human Resources for Ungermann-Bass, a
manufacturer of computer network software and equipment. Prior to 1986, she
spent two years at VLSI Technology, Inc., a semiconductor manufacturer, as human
resources manager. Ms. DeStefano holds a B.A. in Education from the University
of Florida.
Alain J. Labat joined the Company in December 1990 and currently serves
as Senior Vice President, Worldwide Field Operations. Prior to February 1994,
Mr. Labat served as Vice President, International Operations. From 1986 to 1990,
Mr. Labat was employed by Valid Logic Systems, Inc., a CAE company, serving in a
variety of positions, most recently as Vice President of International
Operations. Mr. Labat holds a Master's degree in International Management from
the American Graduate School of International Management, Glendale, Arizona, and
an M.B.A. from INSEEC, Bordeaux, France.
Paul Lippe joined the Company in October 1992 and currently serves as
Senior Vice President, Business Development & Legal, and as Secretary. Mr. Lippe
was previously employed by Solbourne Computer as Vice President, Corporate
Development, General Counsel and Secretary and served as Chairman of the
Colorado Air Quality Control Commission. Mr. Lippe currently is Co-Chairman of
the Peninsula Association of General Counsels. Mr. Lippe holds a B.A. from Yale
College and a J.D. from Harvard Law School.
A. Brooke Seawell joined the Company in March 1991 and currently serves
as Senior Vice President, Finance and Operations and Chief Financial Officer.
From March 1991 to February 1994, Mr. Seawell served as Vice President, Finance
and Operations and Chief Financial Officer. From July 1983 to March 1991, Mr.
Seawell served as Vice President, Finance and Chief Financial Officer of Weitek
Corporation, a supplier of numeric semiconductors. Mr. Seawell is a Certified
Public Accountant and holds a B.A. in economics and an M.B.A. from Stanford
University.
16
<PAGE> 17
There are no family relationships among any executive officers of the
Company.
PART II
ITEM 5. MARKET FOR REGISTRANT'S COMMON EQUITY AND RELATED STOCKHOLDER
MATTERS
The information required by this item is set forth on page 21 of the
Company's 1996 Annual Report to Stockholders and is incorporated herein by
reference.
ITEM 6. SELECTED FINANCIAL DATA
The information required by this item is set forth on page 20 of the
Company's 1996 Annual Report to Stockholders and is incorporated herein by
reference.
ITEM 7. MANAGEMENT'S DISCUSSION AND ANALYSIS OF FINANCIAL CONDITION AND
RESULTS OF OPERATIONS
The information required by this item is set forth on pages 22 through
28 of the Company's 1996 Annual Report to Stockholders and is incorporated
herein by reference.
ITEM 8. FINANCIAL STATEMENTS AND SUPPLEMENTARY DATA
The consolidated financial statements required by this item are
included on pages 30 through 42 of the Company's 1996 Annual Report to
Stockholders and are incorporated by reference. With the exception of the
aforementioned information and the information incorporated in Items 5, 6 and 7,
the Company's 1996 Annual Report to Stockholders is not to be deemed filed as
part of this Form 10-K Annual Report. The report of the Company's Independent
Auditors on the Company's consolidated financial statements is included on page
29 of the Company's 1996 Annual Report to Stockholders and is incorporated by
reference. The report of the Company's Independent Auditors on the financial
statement schedule required by this item is included herein on page 23.
ITEM 9. CHANGES IN AND DISAGREEMENTS WITH ACCOUNTANTS ON ACCOUNTING AND
FINANCIAL DISCLOSURE
Not applicable.
PART III
ITEM 10. DIRECTORS AND EXECUTIVE OFFICERS OF THE REGISTRANT
Information with respect to Directors is included under the caption
"Proposal One -- Election of Directors" in the Company's Notice of Annual
Meeting and Proxy Statement for the Company's annual meeting of stockholders to
be held on February 28, 1997 and is incorporated herein by reference.
Information with respect to Executive Officers is included under the heading
"Executive Officers of the Company" in Part I hereof after Item 4.
Information regarding delinquent filers pursuant to Item 405 of
Regulation S-K is included under the heading "Compliance with Section 16(a) of
the Securities Exchange Act of
17
<PAGE> 18
1934" under the caption "Additional Information" in the Company's Notice of
Annual Meeting of Stockholders and Proxy Statement for the Company's annual
meeting of stockholders to be held on February 28, 1997 and is incorporated
herein by reference.
ITEM 11. EXECUTIVE COMPENSATION
The information required by this item is included under the heading
"Executive Compensation" under the caption "Proposal One -- Election of
Directors" in the Company's Notice of Annual Meeting and Proxy Statement for the
Company's annual meeting of stockholders to be held on February 28, 1997 and is
incorporated herein by reference.
ITEM 12. SECURITY OWNERSHIP OF CERTAIN BENEFICIAL OWNERS AND MANAGEMENT
The information required by this item is included under the heading
"Security Ownership of Certain Beneficial Owners and Management" under the
caption "Proposal One -- Election of Directors" in the Company's Notice of
Annual Meeting and Proxy Statement for the Company's annual meeting of
stockholders to be held on February 28, 1997 and is incorporated herein by
reference.
ITEM 13. CERTAIN RELATIONSHIPS AND RELATED TRANSACTIONS
Not applicable.
18
<PAGE> 19
PART IV
ITEM 14. EXHIBITS, FINANCIAL STATEMENT SCHEDULES, AND
REPORTS ON FORM 8-K.
(a) THE FOLLOWING DOCUMENTS ARE FILED AS PART OF THIS FORM 10-K ANNUAL
REPORT:
1. Financial Statements
The following documents are included in the Company's 1996 Annual
Report to Stockholders and incorporated by reference in Item 8:
<TABLE>
<CAPTION>
Page No. in
Annual Report
<S> <C>
Report of Independent Auditors 29
Consolidated Statements of Income for the years
ended September 30, 1994, 1995 and 1996 30
Consolidated Balance Sheets at September 30, 1995 and 1996 31
Consolidated Statements of Stockholders' Equity for
the years ended September 30, 1994, 1995 and 1996 32
Consolidated Statements of Cash Flows for the years
ended September 30, 1994, 1995 and 1996 33
Notes to Consolidated Financial Statements 34-42
</TABLE>
2. Financial Statement Schedule
The following schedule of the Company is included herein:
Valuation and Qualifying Accounts and Reserves (Schedule II)
All other schedules are omitted because they are not applicable or the
amounts are immaterial or the required information is presented in the
consolidated financial statements or notes thereto.
The following document is included herein:
Independent Auditors' Report on Financial Statement Schedule of
Synopsys, Inc. (page 23)
3. Exhibits
See Item 14(c) below. The following compensatory plans are required to
be filed as exhibits (and have been incorporated by reference from
prior filings, as indicated under Item 14 (c)):
Exhibit 99.1 -- 1992 Stock Option Plan, as restated and amended
Exhibit 99.2 -- Employee Stock Purchase Program, as restated and
amended
Exhibit 99.3 -- International Employee Stock Purchase Program, as
restated and amended
19
<PAGE> 20
(b) REPORTS ON FORM 8-K
Not applicable.
(c) EXHIBITS
Exhibit
Number Description
- --------------------------------------------------------------------------------
10.25 Amendment No. 5 to Lease, dated October 4, 1995, to Lease Agreement
dated August 17, 1990, between the Company and John Arrillaga,
Trustee, or his successor trustee, UTA dated 7/20/77 (Arrillaga
Family Trust), and Richard T. Peery, Trustee, or his successor
trustee, UTA dated 7/20/77 (Richard T. Peery Separate Property
Trust), as amended(1)
10.26 Amendment No. 3 to Lease, dated October 4, 1995, to Lease Agreement
dated June 16, 1992, between the Company and John Arrillaga,
Trustee, or his successor trustee, UTA dated 7/20/77 (Arrillaga
Family Trust), and Richard T. Peery, Trustee, or his successor
trustee, UTA dated 7/20/77 (Richard T. Peery Separate Property
Trust), as amended(1)
10.27 Amendment No. 2 to Lease, dated October 4, 1995, to Lease Agreement
dated June 23, 1993, between the Company and John Arrillaga,
Trustee, or his successor trustee, UTA dated 7/20/77 (Arrillaga
Family Trust), and Richard T. Peery, Trustee, or his successor
trustee, UTA dated 7/20/77 (Richard T. Peery Separate Property
Trust), as amended(1)
10.28 Lease dated January 2, 1996 between the Company and Tarigo-Paul, a
California Limited Partnership(2)
13.1 Portions of the Annual Report to Stockholders for fiscal year ended
September 30, 1996, expressly incorporated by reference herein
21.1 Subsidiaries of the Company
23.1 Consent of KPMG Peat Marwick LLP
24.1 Power of Attorney (see page 22)
27 Financial Data Schedule
99.1 1992 Stock Option Plan, as amended and restated(3)
99.2 Employee Stock Purchase Program, as amended and restated(3)
99.3 International Employee Stock Purchase Plan, as amended and
restated(3)
- --------------------
(1) Incorporated by reference from the Company's Report on Form 10-Q for
the quarterly period ended December 31, 1995
(2) Incorporated by reference from the Company's Report on Form 10-Q for
the quarterly period ended March 31, 1996
(3) Incorporated by reference from the Company's S-8 registration
statement, filed on May 3, 1996
20
<PAGE> 21
SIGNATURES
PURSUANT TO THE REQUIREMENTS OF SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE
ACT OF 1934, THE COMPANY HAS DULY CAUSED THIS REPORT TO BE SIGNED ON ITS BEHALF
BY THE UNDERSIGNED, THEREUNTO DULY AUTHORIZED.
SYNOPSYS, INC.
By /s/ Aart J. de Geus
--------------------------------------------
Aart J. de Geus
President, Chief Executive Officer, and
Director (Principal Executive Officer)
By /s/ A. Brooke Seawell
--------------------------------------------
A. Brooke Seawell
Senior Vice President, Finance and
Operations, and Chief Financial Officer
(Principal Financial and Accounting Officer)
Date: December 20, 1996
21
<PAGE> 22
POWER OF ATTORNEY
KNOW ALL PERSONS BY THESE PRESENTS, that each person whose
signature appears below constitutes and appoints Aart J. de Geus and A. Brooke
Seawell, and each of them, as his true and lawful attorneys-in-fact and agents,
with full power of substitution and resubstitution, for him and in his name,
place and stead, in any and all capacities, to sign any and all amendments
(including post-effective amendments) to this Report on Form 10-K, and to file
the same, with all exhibits thereto, and other documents in connection
therewith, with the Securities and Exchange Commission, granting unto said
attorneys-in-fact and agents, and each of them, full power and authority to do
and perform each and every act and thing requisite and necessary to be done in
connection therewith, as fully to all intents and purposes as he might or could
do in person, hereby ratifying and confirming all that said attorneys-in-fact
and agents, or any of them, or their or his substitute or substitutes, may
lawfully do or cause to be done by virtue hereof.
PURSUANT TO THE REQUIREMENTS OF THE SECURITIES EXCHANGE ACT OF 1934,
THIS REPORT HAS BEEN SIGNED BELOW BY THE FOLLOWING PERSONS ON BEHALF OF THE
REGISTRANT AND IN THE CAPACITIES AND ON THE DATES INDICATED:
/s/ Harvey C. Jones, Jr.
- --------------------------------------- Chairman of the Board of Directors
Harvey C. Jones, Jr. December 20, 1996
/s/ Deborah A. Coleman Director December 20, 1996
- ---------------------------------------
Deborah A. Coleman
/s/ William W. Lattin Director December 20, 1996
- ---------------------------------------
William W. Lattin
/s/ A. Richard Newton Director December 20, 1996
- ---------------------------------------
A. Richard Newton
/s/ Steven C. Walske Director December 20, 1996
- ---------------------------------------
Steven C. Walske
22
<PAGE> 23
INDEPENDENT AUDITORS' REPORT
To the Board of Directors and
Stockholders of Synopsys, Inc.:
Under date of October 18, 1996, we reported on the consolidated balance sheets
of Synopsys, Inc. and subsidiaries as of September 30, 1995 and 1996, and the
related consolidated statements of income, stockholders' equity, and cash flows
for each of the years in the three-year period ended September 30, 1996, which
are included in the annual report to stockholders of Synopsys, Inc. In
connection with our audits of the aforementioned consolidated financial
statements, we also audited the related consolidated financial statement
schedule included in the Form 10-K for the year ended September 30, 1996 of
Synopsys, Inc. This financial statement schedule is the responsibility of the
Company's management. Our responsibility is to express an opinion on this
financial statement schedule based on our audits.
In our opinion, such financial statement schedule, when considered in relation
to the basic consolidated financial statements taken as a whole, presents
fairly, in all material respects, the information set forth therein.
KPMG Peat Marwick LLP
Palo Alto, California
October 18, 1996
23
<PAGE> 24
SCHEDULE II
SYNOPSYS, INC.
VALUATION AND QUALIFYING ACCOUNTS AND RESERVES
(in thousands)
<TABLE>
<CAPTION>
Balance at Additions Charged Balance at
Beginning Charged to to Other End of
of Period Income Accounts(1) Deductions(2) Period
--------- ------ ----------- ------------- ------
Allowance for Doubtful
Accounts and Sales Returns:
<S> <C> <C> <C> <C> <C>
1996 $2,813 $1,576 $ (334) $ (394) $3,661
------ ------ ------ ------ ------
1995 $1,900 $ 688 $ 210 $ (15) $2,813
------ ------ ------ ------ ------
1994 $1,391 $ 443 $ 36 $ (30) $1,900
------ ------ ------ ------ ------
</TABLE>
- --------
(1) Translation and other adjustments.
(2) Accounts written off, net of recoveries.
24
<PAGE> 1
EXHIBIT 13.1
Selected Five-Year Financial Data
<TABLE>
<CAPTION>
(IN THOUSANDS,
EXCEPT PER SHARE AND EMPLOYEE DATA) YEAR ENDED SEPTEMBER 30,
1992 1993 1994 1995 1996
- -----------------------------------------------------------------------------------------------------
<S> <C> <C> <C> <C> <C>
INCOME STATEMENT DATA: (A)
Revenue:
Product $ 71,504 $104,777 $136,475 $180,873 $232,683
Service 20,185 37,926 62,725 84,627 120,817
-------------------------------------------------------
Total revenue 91,689 142,703 199,200 265,500 353,500
-------------------------------------------------------
Cost of revenue:
Product 12,257 13,617 14,374 15,570 16,510
Service 6,364 9,687 13,398 15,039 22,383
-------------------------------------------------------
Total cost of revenue 18,621 23,304 27,772 30,609 38,893
-------------------------------------------------------
Gross margin 73,068 119,399 171,428 234,891 314,607
Operating expenses:
Research and development 15,113 25,382 41,301 58,673 84,248
Sales and marketing 38,566 58,975 78,181 101,980 134,086
General and administrative 10,080 12,549 17,046 22,238 27,673
Merger-related costs 1,374 -- 7,400 -- --
In-process research and development -- -- 5,900 9,200 39,700
-------------------------------------------------------
Total operating expenses 65,133 96,906 149,828 192,091 285,707
-------------------------------------------------------
Operating income 7,935 22,493 21,600 42,800 28,900
Other income, net 781 956 2,054 4,908 6,950
-------------------------------------------------------
Income before income taxes 8,716 23,449 23,654 47,708 35,850
Income tax provision 4,118 8,448 9,449 17,408 12,150
-------------------------------------------------------
Net income $ 4,598 $ 15,001 $ 14,205 $ 30,300 $ 23,700
-------------------------------------------------------
Earnings per share (B) $ .13 $ .41 $ .36 $ .75 $ .57
-------------------------------------------------------
Weighted average common shares
and equivalents where dilutive (B) 34,508 36,854 39,038 40,416 41,553
-------------------------------------------------------
BALANCE SHEET DATA: (A)
Cash and short-term investments $ 49,814 $ 95,013 $141,213 $209,984 $236,567
Working capital 41,260 64,098 94,756 147,259 157,377
Total assets 101,536 144,389 211,949 297,571 408,967
Long-term obligations 778 -- -- -- 15,970
Total stockholders' equity 63,061 89,364 123,728 182,302 232,747
OTHER DATA:
Permanent employees 621 812 1,060 1,388 1,716
</TABLE>
(A) SEE NOTE 3 OF NOTES TO CONSOLIDATED FINANCIAL STATEMENTS REGARDING THE
COMPANY'S MERGERS WITH LOGIC MODELING CORPORATION AND SILICON ARCHITECTS.
(B) SHARE AND PER SHARE AMOUNTS HAVE BEEN RESTATED FOR ALL PERIODS PRESENTED TO
REFLECT THE TWO-FOR-ONE STOCK SPLIT EFFECTIVE SEPTEMBER 8, 1995.
<PAGE> 2
Selected Unaudited Quarterly Financial Data (A)
<TABLE>
<CAPTION>
YEAR ENDED SEPTEMBER 30, 1995 YEAR ENDED SEPTEMBER 30, 1996
(IN THOUSANDS, EXCEPT PER SHARE DATA) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
<S> <C> <C> <C> <C> <C> <C> <C> <C>
Revenue:
Product $40,009 $43,707 $47,088 $50,069 $53,749 $56,980 $58,612 $63,342
Service 19,891 20,293 21,012 23,431 25,251 28,020 32,388 35,158
---------------------------------------------------------------------------
Total revenue 59,900 64,000 68,100 73,500 79,000 85,000 91,000 98,500
---------------------------------------------------------------------------
Cost of revenue:
Product 3,190 5,190 3,364 3,826 3,593 3,930 4,302 4,685
Service 3,408 3,081 3,994 4,556 4,741 5,263 6,240 6,139
---------------------------------------------------------------------------
Total cost of revenue 6,598 8,271 7,358 8,382 8,334 9,193 10,542 10,824
---------------------------------------------------------------------------
Gross margin 53,302 55,729 60,742 65,118 70,666 75,807 80,458 87,676
Operating expenses:
Research and development 13,232 13,505 15,261 16,675 18,202 20,441 21,921 23,684
Sales and marketing 23,447 24,632 26,202 27,699 30,323 32,599 34,032 37,132
General and administrative 4,923 5,492 5,779 6,044 6,341 6,467 7,005 7,860
In-process research and development -- -- 9,200 -- -- 39,700 -- --
---------------------------------------------------------------------------
Total operating expenses 41,602 43,629 56,442 50,418 54,866 99,207 62,958 68,676
---------------------------------------------------------------------------
Operating income (loss) 11,700 12,100 4,300 14,700 15,800 (23,400) 17,500 19,000
Other income, net 639 1,169 1,500 1,600 1,850 1,700 1,700 1,700
---------------------------------------------------------------------------
Income (loss) before income taxes 12,339 13,269 5,800 16,300 17,650 (21,700) 19,200 20,700
Income tax provision (benefit) 4,533 4,951 2,088 5,836 6,000 (7,400) 6,528 7,022
---------------------------------------------------------------------------
Net income (loss) $ 7,806 $ 8,318 $ 3,712 $ 10,464 $ 11,650 $(14,300) $12,672 $13,678
Earnings (loss) per share (B) $ 0.20 $ 0.21 $ 0.09 $ 0.25 $ 0.28 $ (0.36) $ 0.30 $ 0.32
---------------------------------------------------------------------------
Weighted average common shares
and equivalents where dilutive (B) 39,554 40,050 40,760 41,299 41,632 39,494 42,556 42,530
---------------------------------------------------------------------------
Market price range (B)
High $24.25 $27.38 $31.38 $34.50 $38.50 $37.75 $46.75 $50.50
Low $19.75 $21.38 $23.50 $28.13 $23.00 $27.50 $29.75 $30.75
AS A PERCENTAGE OF TOTAL REVENUE
Revenue:
Product 67% 68% 69% 68% 68% 67% 64% 64%
Service 33 32 31 32 32 33 36 36
---------------------------------------------------------------------------
Total revenue 100 100 100 100 100 100 100 100
Cost of revenue:
Product 5 8 5 5 5 5 5 5
Service 6 5 6 6 6 6 7 6
---------------------------------------------------------------------------
Total cost of revenue 11 13 11 11 11 11 12 11
---------------------------------------------------------------------------
Gross margin 89 87 89 89 89 89 88 89
Operating expenses:
Research and development 22 21 22 23 23 24 24 24
Sales and marketing 39 38 38 38 38 38 37 38
General and administrative 8 9 9 8 8 8 8 8
In-process research and development -- -- 14 -- -- 47 -- --
---------------------------------------------------------------------------
Total operating expenses 69 68 83 69 69 117 69 70
---------------------------------------------------------------------------
Operating income (loss) 20 19 6 20 20 (28) 19 19
Other income, net 1 2 2 2 2 2 2 2
---------------------------------------------------------------------------
Income (loss) before income taxes 21 21 8 22 22 (26) 21 21
Income tax provision (benefit) 8 8 3 8 7 (9) 7 7
---------------------------------------------------------------------------
Net income (loss) 13% 13% 5% 14% 15% (17)% 14% 14%
</TABLE>
(A) SEE NOTE 3 OF NOTES TO CONSOLIDATED FINANCIAL STATEMENTS REGARDING THE
COMPANY'S MERGER WITH SILICON ARCHITECTS.
(B) THE COMPANY'S COMMON STOCK IS TRADED IN THE OVER-THE-COUNTER MARKET ON THE
NASDAQ NATIONAL MARKET SYSTEM UNDER THE SYMBOL "SNPS." AT OCTOBER 31, 1996,
THERE WERE APPROXIMATELY 277 OWNERS OF RECORD OF THE COMPANY'S COMMON STOCK. THE
COMPANY HAS NOT PAID CASH DIVIDENDS AND DOES NOT ANTICIPATE PAYING CASH
DIVIDENDS IN THE FORESEEABLE FUTURE. SHARE AND PER SHARE AMOUNTS HAVE BEEN
RESTATED FOR ALL PERIODS PRESENTED TO REFLECT THE TWO-FOR-ONE STOCK SPLIT
EFFECTIVE SEPTEMBER 8, 1995.
<PAGE> 3
Management's Discussion and Analysis of
Financial Condition and Results of Operations
RESULTS OF OPERATIONS
The following table sets forth operating results as a percentage of total
revenue for fiscal 1994, 1995, and 1996 and the percentage change of such
results compared to the prior year.
<TABLE>
<CAPTION>
PERCENTAGE OF TOTAL REVENUE PERCENTAGE CHANGE
1994 1995 1996 1994-1995 1995-1996
<S> <C> <C> <C> <C> <C>
Revenue:
Product 69% 68% 66% 33% 29%
Service 31 32 34 35 43
---------------------------
Total revenue 100 100 100 33 33
---------------------------
Cost of revenue:
Product 7 6 5 8 6
Service 7 6 6 12 49
---------------------------
Total cost of revenue 14 12 11 10 27
---------------------------
Gross margin 86 88 89 37 34
Operating expenses:
Research and development 21 22 24 42 44
Sales and marketing 39 38 38 30 31
General and administrative 8 8 8 30 24
Merger-related costs 4 -- -- (100) --
In-process research and development 3 4 11 56 332
---------------------------
Total operating expenses 75 72 81 28 49
---------------------------
Operating income 11 16 8 98 (32)
Other income, net 1 2 2 139 42
---------------------------
Income before income taxes 12 18 10 102 (25)
Income tax provision 5 7 3 84 (30)
---------------------------
Net income 7% 11% 7% 113% (22)%
</TABLE>
Except for the historical information presented, the following discussion
contains forward-looking statements that involve risks and uncertainties. The
Company's actual results could differ materially from those discussed herein.
Factors that could cause or contribute to such differences include, but are not
limited to, those discussed below in "Factors That May Affect Future Results."
Corporate agreements, relationships, and acquisitions of complementary
businesses are part of the Company's overall business strategy. Technical
relationships and acquisitions accommodate the Company's focused strategic
requirements by filling gaps in existing products or technologies and providing
the Company with an avenue into new lines of business. The Company will continue
to evaluate potential alliances which could result in additional business
combinations and corporate relationships in the future. There can be no
assurance that the Company will be successful in these efforts.
CORPORATE AGREEMENTS AND RELATIONSHIPS
On February 1, 1996, the Company and International Business Machines Corporation
(IBM) entered into a six-year Joint Development and License Agreement Concerning
EDA Software and Related Intellectual Property (the Agreement). Pursuant to the
Agreement, the Company
<PAGE> 4
acquired certain in-process research and development technology and a
non-exclusive license to sublicense and to use certain existing IBM electronic
design automation (EDA) technology and the underlying intellectual property, and
licensed certain of its EDA-related intellectual property to IBM. In addition,
the Company and IBM are jointly developing new EDA products in the areas of
synthesis, test methodology, design planning, and static timing sign-off. The
Company will have sole ownership of synthesis products and the exclusive right
to market test, design planning, and static timing products (subject to certain
rights of IBM upon termination of the Agreement). In accordance with the
Agreement, the Company paid IBM $11.0 million in cash and issued $30.0 million
in notes, which bear interest at three percent, and are payable to IBM upon the
earlier of achievement of scheduled milestones or at maturity in 2006. The notes
were recorded at fair value of $28.5 million, using a discount rate commensurate
with the risks involved. The Company will also pay royalties on revenues from
the sale of new products developed pursuant to the Agreement. As a result of the
transaction, the Company incurred an in-process research and development charge
of $39.7 million in the second quarter of fiscal 1996.
On May 7, 1996, the Company and Cooper and Chyan Technology, Inc. (CCT), a
developer of routing technology for printed circuit boards and integrated
circuits, entered into a strategic relationship. As part of this strategic
relationship, the Company purchased 1.2 million shares, approximately 9.9
percent of the outstanding shares of CCT, for $14.50 per share. In accordance
with Statement of Financial Accounting Standards (SFAS) No. 115, "Accounting for
Certain Investments in Debt and Equity Securities," the investment has been
classified as "available for sale," and an unrealized gain of $8.3 million, net
of taxes, was recorded as a separate component of stockholders' equity during
fiscal year 1996. CCT and Cadence Design Systems, Inc. recently announced that
they had reached an agreement to merge. The Company is evaluating the effect of
such a merger on its relationship with CCT.
MERGERS AND ACQUISITIONS
On February 16, 1994, the Company issued approximately 5.2 million shares of its
common stock in exchange for all the outstanding shares of capital stock, vested
stock options, and warrants of Logic Modeling Corporation (LMC), a developer of
simulation models and modeling technologies for the verification of electronic
designs. The merger was accounted for as a pooling of interests and,
accordingly, the Company's consolidated financial statements have been restated
for all periods.
On May 31, 1994, the Company acquired all the outstanding stock of Cadis GmbH
(Cadis) for approximately $3.6 million in cash and notes. Cadis was a software
developer specializing in digital signal processing design. On September 30,
1994, the Company acquired all the outstanding stock of Arcad SA (Arcad) for
approximately $1.5 million in cash and notes. Arcad was a software developer of
VHDL models specializing in telecommunications standards. These acquisitions
were accounted for by the purchase method of accounting, and the results of
operations of Cadis and Arcad are included in the Company's consolidated results
of operations since the dates of the acquisitions. The purchase price,
acquisition costs, and net liabilities assumed total $7.3 million, of which $5.9
million was allocated to in-process research and development expense.
On May 10, 1995, the Company issued approximately 1.4 million shares of its
common stock in exchange for all the outstanding shares of capital stock and
warrants of Silicon Architects, a developer of design technology for complex
application specific integrated circuits (ASICs) and application specific
standard products (ASSPs). Additionally, options to acquire shares of Silicon
Architects' common stock were exchanged for options to acquire approximately
148,000 shares of the Company's common stock. The merger was accounted for as a
pooling of interests and, accordingly, the Company's consolidated financial
statements have been restated for all periods.
<PAGE> 5
On June 28, 1995, the Company acquired all the outstanding securities of ARKOS
Design, Inc. (ARKOS) for approximately $9.3 million in cash and notes. The notes
had a balance of $3.1 million at September 30, 1996, mature at various dates
through 2005, contain certain provisions that could accelerate maturity, and are
included in current liabilities. The Company recently introduced a product based
on ARKOS technology that supports high-speed validation of integrated circuits
(ICs). The acquisition was accounted for by the purchase method of accounting,
and the results of operations of ARKOS are included in the Company's
consolidated results since the date of the acquisition. The purchase price,
acquisition costs, and net liabilities assumed total $9.7 million, of which $9.2
million was allocated to in-process research and development expense.
REVENUE
The Company's revenue increased by 33% from $199.2 million in fiscal 1994 to
$265.5 million in fiscal 1995 and by 33% from fiscal 1995 to $353.5 million in
fiscal 1996. The percentage of the Company's total revenue attributable to
software and systems products decreased from 69% in fiscal 1994 to 68% in fiscal
1995 and to 66% in fiscal 1996, primarily due to an increase in the Company's
base of installed software and the associated increase in maintenance and
support, customer training, and consulting revenue. To date, price increases
have not been a material factor in the Company's revenue growth.
Product revenue increased by 33% from $136.5 million in fiscal 1994 to $180.9
million in fiscal 1995 and by 29% from fiscal 1995 to $232.7 million in fiscal
1996. These increases were primarily due to increased worldwide licensing and
sales of the Company's software and systems products.
Service revenue increased by 35% from $62.7 million in fiscal 1994 to $84.6
million in fiscal 1995 and by 43% from fiscal 1995 to $120.8 million in fiscal
1996. These increases were primarily attributable to continued growth of the
installed customer base and the renewal of maintenance and support contracts.
Revenue from international operations was $94.5 million, $138.0 million, and
$173.2 million or 48%, 52%, and 49% of total revenue in fiscal 1994, 1995, and
1996, respectively. The 1996 decrease in international revenue as a percentage
of total revenue was primarily due to decreased revenue in Japan as a percentage
of total revenue, which was attributable to a decline in the value of the yen
versus the dollar.
Revenue consists of fees for licenses and subscriptions of the Company's
software products, sales of systems products, maintenance and support, customer
training, and consulting. License revenue is recognized upon shipment of
products and fulfillment of significant acceptance terms, if any. When the
Company receives advance payment for software products, such payments are
recorded as advances and recognized as revenue when products are actually
shipped. The Company has fulfilled certain orders by shipping the product and
providing a temporary access key for software usage. Revenue is deferred until
the Company provides a production key and collectability is reasonably assured.
Revenue from systems products is recognized upon shipment of products and
fulfillment of significant acceptance terms, if any. Revenue from subscriptions
is deferred and recognized ratably over the term that subscription services are
provided, generally twelve months. Maintenance and support revenue is deferred
and recognized ratably over the term of the maintenance agreement, which is
typically twelve months. Revenue from customer training and consulting is
recognized as the service is performed.
COST OF REVENUE
Cost of product revenue includes cost of production personnel, product
packaging, documentation, amortization of capitalized software development
costs, and costs of the Company's systems products. The cost of internally
developed capitalized software is amortized based on the greater of the ratio of
current product revenue to the total of current and anticipated product revenue
or the straight-line method over the software's estimated economic life of
approximately two years. Cost of product revenue was 7%, 6%, and 5% of total
revenue in fiscal 1994, 1995, and 1996,
<PAGE> 6
respectively. Cost of service revenue includes personnel and the related costs
associated with providing such service. Although service revenue increased as a
percentage of total revenue in each fiscal year presented, cost of service
revenue as a percentage of total revenue was 7% of total revenue in fiscal 1994
and declined to 6% of total revenue in fiscal 1995 and 1996. Cost of product
revenue and cost of service revenue as a percentage of total revenue both
decreased because personnel and related costs increased at a slower rate than
revenue.
RESEARCH AND DEVELOPMENT
The Company believes that significant investment for product research and
development is essential to product and technical leadership. Research and
development expenses increased by 42% from $41.3 million in fiscal 1994 to $58.7
million in fiscal 1995 and by 44% from fiscal 1995 to $84.2 million in fiscal
1996, net of capitalized software development costs. These increases were
primarily attributable to increases in personnel and personnel-related costs
associated with the development of new products and enhancement of existing
products. In addition, during fiscal 1996, the Company incurred hardware
prototype expenses associated with the development of the ARKOS emulation
product. Research and development expenses represented 21%, 22%, and 24% of
total revenue in fiscal 1994, 1995, and 1996, respectively, representing the
Company's ongoing commitment to invest substantial resources in research and
development. The Company expects continued growth in research and development
expenses, provided that the Company is able to continue to hire a sufficient
number of qualified personnel. The Company expects that for fiscal 1997,
research and development expenses as a percentage of total revenue will remain
approximately at the fiscal 1996 level.
The Company capitalizes software development costs after technological
feasibility of the product has been established in accordance with SFAS No. 86.
The Company capitalized software development costs of $1.5 million in fiscal
1994 and $1.0 million in fiscal years 1995 and 1996, which represented
approximately 4%, 2%, and 1% of total research and development expenses, in
fiscal 1994, 1995, and 1996, respectively. See Note 1 of Notes to Consolidated
Financial Statements.
SALES AND MARKETING
Sales and marketing expenses increased by 30% from $78.2 million in fiscal 1994
to $102.0 million in fiscal 1995 and by 31% from fiscal 1995 to $134.1 million
in fiscal 1996. Sales and marketing expenses represented 39% of total revenue in
1994 and 38% of total revenue in both fiscal years 1995 and 1996. Total expenses
increased in each fiscal year due to the expansion of the Company's worldwide
sales and marketing organizations, higher incentive compensation associated with
increased revenue, and participation in domestic and international conferences
and trade shows. The Company expects that for fiscal 1997, sales and marketing
expenses as a percentage of total revenue will be at or slightly lower than the
fiscal 1996 level.
GENERAL AND ADMINISTRATIVE
General and administrative expenses increased by 30% from $17.0 million in
fiscal 1994 to $22.2 million in fiscal 1995 and by 24% from fiscal 1995 to $27.7
million in fiscal 1996. General and administrative expenses represented 8% of
total revenue in each of the three years presented. Expenses increased primarily
due to an increase in personnel and the investment associated with the
implementation of an enterprise-wide database and management information system,
based principally on software from SAP AG. The Company expects that for fiscal
1997, general and administrative expenses as a percentage of total revenue will
be at or slightly lower than the fiscal 1996 level.
<PAGE> 7
MERGER-RELATED COSTS
In fiscal 1994, in connection with the LMC merger, the Company recorded related
costs of approximately $7.4 million, primarily for transaction costs and
elimination of duplicate facilities and equipment. These estimated costs were
reduced by $900,000 in fiscal 1995.
In fiscal 1995, in connection with the Silicon Architects merger, the Company
recorded related costs of approximately $900,000. These nonrecurring costs
primarily consisted of contract cancellation charges, transaction fees, and the
elimination of duplicate facilities and equipment.
OTHER INCOME
Other income consists of interest income, interest expense, and miscellaneous
income and expense items. Other income was $2.1 million, $4.9 million, and $7.0
million in fiscal 1994, 1995, and 1996, respectively. Other income increased in
each fiscal year primarily as a result of earnings on higher cash and short-term
investment balances. In fiscal 1996, interest expense increased due primarily to
the notes associated with the IBM Agreement.
INCOME TAX PROVISION
The provision for income taxes was $9.4 million, $17.4 million, and $12.2
million in fiscal 1994, 1995, and 1996, respectively. The provision for income
taxes as a percentage of pretax income was 40%, 36%, and 34% in fiscal 1994,
1995, and 1996, respectively. The tax rate in fiscal 1994 was higher than the
rates in fiscal 1995 and 1996 primarily due to items related to mergers and
acquisitions.
NET INCOME
The Company reported net income of $14.2 million, $30.3 million, and $23.7
million, or 7%, 11%, and 7% of total revenue in fiscal 1994, 1995, and 1996,
respectively.
LIQUIDITY AND CAPITAL RESOURCES
As of September 30, 1996, Synopsys had $236.6 million of cash and short-term
investments available to finance future growth. In fiscal 1996, cash and
short-term investments increased by $26.6 million primarily attributable to cash
flows from operations of $88.3 million, and proceeds from the sale of common
stock of $28.0 million. These positive cash flows were partially off-set by
capital expenditures of $39.2 million, the investment in Cooper and Chyan
Technology of $17.5 million, cash paid in relation to the IBM Agreement of $11.5
million, and the repurchase of common stock of $14.8 million.
In May 1996, the Company announced that its Board of Directors had authorized
the repurchase of up to 2.0 million shares of its outstanding common stock in
the open market over the next 24 months. During fiscal 1996, the Company
purchased 361,494 shares at an average price of approximately $41.00 per share.
The repurchased shares are available for use under the Company's employee stock
plans and for other corporate purposes. All shares repurchased during fiscal
1996 were reissued by the end of the year.
The Company also had available three foreign exchange lines of credit totaling
$169.0 million to facilitate foreign currency transactions. The Company enters
into forward exchange contracts to hedge foreign currency denominated
intercompany balances. Gains and losses on contracts to hedge foreign currency
commitments are recognized during the periods in which the related instruments
are outstanding. At September 30, 1996, the Company had outstanding forward
contracts in yen and European currencies totaling approximately $4.1 million.
The forward exchange contracts are valued at prevailing market rates.
The Company believes that its current cash balances, anticipated cash flows from
operations and the existing credit facilities will be sufficient to fund the
Company's cash needs for at least the next twelve months.
<PAGE> 8
FACTORS THAT MAY AFFECT FUTURE RESULTS
When used in the following discussion, the words "projects," "expects," and
similar expressions are intended to identify forward-looking statements. Such
statements, and the Company's results, are subject to certain risks and
uncertainties, including those discussed below, that could cause actual results
to differ materially from those projected or estimated.
The EDA industry is highly competitive. The Company's products compete with
similar products from other vendors and compete with other EDA products and
services for a share of the EDA budgets of their customers. Historically, much
of the Company's growth has been attributable to the strength of its synthesis
products, a market segment in which the Company is currently the leading
supplier. Opportunities for growth in market share in this segment are limited.
The EDA industry as a whole is experiencing rapid change. Technology advances
and market requirements are fueling a change in the nature of competition among
EDA vendors. Advances in semiconductor technology are expected to create a need
for tighter integration between logic design and physical design, and companies
will increasingly compete over "design flows" involving a broad range of
products and services rather than individual design tools.
No single EDA company currently offers its customers industry leading products
for a complete design flow. Presently, the Company does not offer physical
design tools, a market which is currently dominated by Cadence Design Systems,
Inc. and Avant! Corporation, and trails Cadence in its capacity to offer design
services. In May 1996, the Company entered into a strategic relationship with
Cooper & Chyan Technology, Inc. (CCT) to link the Company's existing synthesis
products and its design planning products under development with CCT's routing
technology. Cadence and CCT have announced their intention to merge. The Company
is evaluating the effect of such a merger on its relationship with CCT.
The Company is seeking to develop a balanced product portfolio. Among the most
important new products offered by the Company are its Behavioral Compiler,
Cell-Based Array, ARKOS hardware emulator, and Cyclone simulation accelerator
products. These products have achieved initial market acceptance, but the
Company will only derive significant revenue from these products if they are
accepted by a broad range of customers, which cannot be assured.
The Company's business has benefited from the rapid worldwide growth of the
semiconductor industry. The semiconductor industry grew relatively slowly for
most of 1996. Despite recent reports of improving conditions in the industry,
the outlook for 1997 remains uncertain. Slower growth in the semiconductor
industry could have an adverse effect on the Company's performance.
The Company attempts to manage its business to achieve quarter-to-quarter
revenue and earnings growth. The ability to manage such growth is affected by a
number of factors, including customer product demand, product license terms, the
size of the Company's backlog, and decisions regarding the timing of revenue
recognition. In recent years, the management of revenue and earnings growth has
become more difficult as a result of a number of factors. The Company's orders
have become more seasonal, with higher volumes in the second and fourth quarters
of the Company's fiscal year, and disproportionately weighted toward the latter
part of the quarter. The average order size has also increased. In addition, an
increasing amount of the Company's orders involve products and services which
yield revenue over multiple quarters (often extending beyond the current fiscal
year) or at the end of the contract rather than at the time of sale, including
time-based product licenses, consulting services, development contracts, and CBA
licenses and royalties. Because of these trends, the Company's ability to
convert backlog to revenue in any quarter is less certain than it historically
has been, despite an increase in overall backlog levels. It is possible for the
Company to experience historical levels of orders growth while experiencing a
slower rate of revenue and earnings growth. Conversely, for
<PAGE> 9
a given quarter it is also possible for the Company to maintain steady revenue
and earnings growth while experiencing a slower rate of orders growth.
Ultimately, long-term revenue and earnings growth is dependent upon the
successful development and sale of the Company's products and services over a
sustained period of time.
The Company's operating expenses are based in part on its expectations of future
revenue, and expense levels are generally committed in advance of revenue. The
Company continues to expand and increase its operating expenses in order to
generate and support additional revenue in the future. If revenue does not
materialize as expected, the Company's results of operations are likely to be
adversely affected. Net income may be disproportionately affected by a reduction
in revenue because only a small portion of the Company's expenses varies with
its revenue.
In recent years, international revenue has accounted for approximately half of
the Company's revenue. As a result, the Company's financial performance could be
negatively affected by such factors as changes in foreign currency exchange
rates and changes in regional or worldwide economic or political conditions. In
particular, revenue from sales in Japan during fiscal 1996 was adversely
affected by a decline in the value of the yen against the dollar. Continued
weakness in the value of the yen could adversely affect revenue from Japan
during fiscal year 1997.
In February 1996, the Company entered into a six-year joint development and
license agreement with IBM, pursuant to which the Company and IBM will jointly
develop certain new products that the Company believes are important to the
long-term growth of its business. The Company has not previously entered into a
joint development agreement of this scope. Joint development of products is
subject to risks and uncertainties over and above those affecting internal
development, and there can be no assurance that the Company's joint development
efforts will be successful.
The Company's success is dependent on technical and other contributions of key
individuals, and there can be no assurance that the Company can continue to
recruit and retain such key personnel.
The Company's stock price, like that of other technology companies, is subject
to significant volatility. Past financial performance should not be considered a
reliable indicator of future performance, and investors should not use
historical trends to anticipate results or trends in future periods. If revenues
or earnings in any quarter fail to meet expectations of the investment
community, there could be an immediate and significant impact on the Company's
stock price. In addition, the Company's stock price may be affected by broader
market trends that may be unrelated to the Company's performance.
The preparation of financial statements in conformity with generally accepted
accounting principles requires management to make estimates and assumptions that
affect the recorded amounts of assets and liabilities, disclosure of those
assets and liabilities at the date of the financial statements and the recorded
amounts of expenses during the reporting period. A change in the facts and
circumstances surrounding these estimates could result in a change to the
estimates and impact future operating results.
<PAGE> 10
Report of Independent Auditors
TO THE BOARD OF DIRECTORS
AND STOCKHOLDERS OF SYNOPSYS, INC.:
We have audited the accompanying consolidated balance sheets of Synopsys, Inc.
and subsidiaries as of September 30, 1995 and 1996, and the related consolidated
statements of income, stockholders' equity and cash flows for each of the years
in the three-year period ended September 30, 1996. These consolidated financial
statements are the responsibility of the Company's management. Our
responsibility is to express an opinion on these consolidated financial
statements based on our audits.
We conducted our audits in accordance with generally accepted auditing
standards. Those standards require that we plan and perform the audit to obtain
reasonable assurance about whether the financial statements are free of material
misstatement. An audit includes examining, on a test basis, evidence supporting
the amounts and disclosures in the financial statements. An audit also includes
assessing the accounting principles used and significant estimates made by
management, as well as evaluating the overall financial statement presentation.
We believe that our audits provide a reasonable basis for our opinion.
In our opinion, based on our audits, the consolidated financial statements
referred to above present fairly, in all material respects, the financial
position of Synopsys, Inc. and subsidiaries as of September 30, 1995 and 1996,
and the results of their operations and their cash flows for each of the years
in the three-year period ended September 30, 1996, in conformity with generally
accepted accounting principles.
KPMG Peat Marwick LLP
Palo Alto, California
October 18, 1996
<PAGE> 11
Consolidated Statements of Income
<TABLE>
<CAPTION>
YEAR ENDED SEPTEMBER 30,
(IN THOUSANDS, EXCEPT PER SHARE DATA) 1994 1995 1996
- -------------------------------------------------------------------------------------------------
<S> <C> <C> <C>
Revenue:
Product $136,475 $180,873 $232,683
Service 62,725 84,627 120,817
-------------------------------------------
Total revenue 199,200 265,500 353,500
-------------------------------------------
Cost of revenue:
Product 14,374 15,570 16,510
Service 13,398 15,039 22,383
-------------------------------------------
Total cost of revenue 27,772 30,609 38,893
-------------------------------------------
Gross margin 171,428 234,891 314,607
Operating expenses:
Research and development 41,301 58,673 84,248
Sales and marketing 78,181 101,980 134,086
General and administrative 17,046 22,238 27,673
Merger-related costs 7,400 -- --
In-process research and development 5,900 9,200 39,700
-------------------------------------------
Total operating expenses 149,828 192,091 285,707
-------------------------------------------
Operating income 21,600 42,800 28,900
-------------------------------------------
Other income (expense):
Interest income 3,035 6,282 8,509
Interest and other expense (981) (1,374) (1,559)
-------------------------------------------
Total other income 2,054 4,908 6,950
-------------------------------------------
Income before income taxes 23,654 47,708 35,850
Income tax provision 9,449 17,408 12,150
-------------------------------------------
Net income $ 14,205 $ 30,300 $ 23,700
-------------------------------------------
Earnings per share $ .36 $ .75 $ .57
-------------------------------------------
Weighted average common shares
and equivalents where dilutive 39,038 40,416 41,553
</TABLE>
See accompanying notes.
<PAGE> 12
Consolidated Balance Sheets
<TABLE>
<CAPTION>
SEPTEMBER 30,
(IN THOUSANDS, EXCEPT SHARE DATA) 1995 1996
- -----------------------------------------------------------------------------------------------------------------------
<S> <C> <C>
ASSETS
Current assets:
Cash and cash equivalents $ 91,193 $ 33,904
Short-term investments 118,791 202,663
--------------------------
Cash and short-term investments 209,984 236,567
Accounts receivable, net of allowances of $2,813 and $3,661, respectively 42,863 61,085
Prepaid expenses, deferred taxes and other 9,681 19,975
--------------------------
Total current assets 262,528 317,627
--------------------------
Property and equipment, net 28,720 51,537
Capitalized software development costs, net of accumulated amortization
of $1,680 and $2,805, respectively 1,271 1,146
Long-term investment -- 30,495
Other assets 5,052 8,162
--------------------------
Total assets $297,571 $408,967
==========================
LIABILITIES AND STOCKHOLDERS' EQUITY
Current liabilities:
Accounts payable $ 8,563 $ 11,509
Accrued liabilities 40,181 59,072
Current portion of long-term debt 4,061 11,580
Income taxes payable 9,908 12,091
Deferred revenue 52,556 65,998
--------------------------
Total current liabilities 115,269 160,250
--------------------------
Long-term debt -- 15,970
Commitments
Stockholders' equity:
Preferred stock, $.01 par value; 2,000,000 shares authorized
and no shares outstanding -- --
Common stock, $.01 par value; 100,000,000 shares authorized;
38,970,504 and 40,434,563 shares outstanding, respectively 390 404
Additional paid-in capital 124,322 152,187
Retained earnings 57,838 72,257
Cumulative translation adjustment (248) (402)
Net unrealized gain on investment -- 8,301
--------------------------
Total stockholders' equity 182,302 232,747
--------------------------
Total liabilities and stockholders' equity $297,571 $408,967
==========================
</TABLE>
SEE ACCOMPANYING NOTES.
<PAGE> 13
Consolidated Statements of Stockholders' Equity
<TABLE>
<CAPTION>
(IN THOUSANDS, ADDITIONAL CUMULATIVE UNREALIZED
EXCEPT SHARE DATA) COMMON STOCK PAID-IN RETAINED TRANSLATION GAIN ON TREASURY
SHARES AMOUNT CAPITAL EARNINGS ADJUSTMENT INVESTMENT STOCK TOTAL
- ----------------------------------------------------------------------------------------------------------------------------------
<S> <C> <C> <C> <C> <C> <C> <C> <C>
Balance at
September 30, 1993 33,667,696 $ 337 $ 77,001 $ 12,786 $(760) $ -- $ -- $ 89,364
Merger with Silicon
Architects 1,095,995 11 602 547 -- -- -- 1,160
Issuance of Silicon
Architects' common stock
prior to the merger 247,476 3 2,981 -- -- -- -- 2,984
Net exercise of warrants 39,398 -- 173 -- -- -- -- 173
Stock issued under stock
option and stock purchase
plans 2,019,334 20 8,974 -- -- -- -- 8,994
Tax benefit associated with
exercise of stock options -- -- 6,700 -- -- -- -- 6,700
Translation adjustment -- -- -- -- 148 -- -- 148
Net income -- -- -- 14,205 -- -- -- 14,205
--------------------------------------------------------------------------------------------------
Balance at
September 30, 1994 37,069,899 371 96,431 27,538 (612) -- -- 123,728
Net exercise of warrants 7,432 -- 90 -- -- -- -- 90
Stock issued under stock
option and stock purchase
plans 1,893,173 19 19,701 -- -- -- -- 19,720
Tax benefit associated with
exercise of stock options -- -- 8,100 -- -- -- -- 8,100
Translation adjustment -- -- -- -- 364 -- -- 364
Net income -- -- -- 30,300 -- -- -- 30,300
--------------------------------------------------------------------------------------------------
Balance at
September 30, 1995 38,970,504 390 124,322 57,838 (248) -- -- 182,302
Acquisition of treasury
stock (361,494) -- -- -- -- -- (14,817) (14,817)
Stock issued under stock
option and stock purchase
plans 1,825,553 14 22,424 (9,281) -- -- 14,817 27,974
Tax benefit associated with
exercise of stock options -- -- 5,441 -- -- -- -- 5,441
Translation adjustment -- -- -- -- (154) -- -- (154)
Net unrealized gain on
investment -- -- -- -- -- 8,301 -- 8,301
Net income -- -- -- 23,700 -- -- -- 23,700
--------------------------------------------------------------------------------------------------
Balance at
September 30, 1996 40,434,563 $ 404 $152,187 $ 72,257 $(402) $8,301 $ -- $ 232,747
==================================================================================================
</TABLE>
SEE ACCOMPANYING NOTES.
<PAGE> 14
Consolidated Statements of Cash Flows
<TABLE>
<CAPTION>
YEAR ENDED SEPTEMBER 30,
(IN THOUSANDS) 1994 1995 1996
- ---------------------------------------------------------------------------------------------------------
<S> <C> <C> <C>
Cash flows from operating activities:
Net income $ 14,205 $ 30,300 $ 23,700
Adjustments to reconcile net income to net cash provided
by operating activities:
Depreciation and amortization 12,213 15,548 18,721
Interest accretion on notes payable -- -- 470
Provision for doubtful accounts and sales returns 443 913 848
Tax benefit associated with stock options 6,700 8,100 5,441
Deferred revenue 16,635 10,731 13,442
Deferred taxes (900) (1,725) (11,944)
Merger-related costs 3,724 -- --
In-process research and development 5,900 9,200 39,700
Net changes in operating assets and liabilities:
Accounts receivable (13,343) (9,078) (19,070)
Prepaid expenses and other (2,148) (105) (3,019)
Other assets (1,967) 793 (3,129)
Accounts payable (594) 927 2,946
Accrued liabilities 12,290 4,156 17,993
Income taxes payable 624 6,960 2,183
-------------------------------------
Net cash provided by operating activities 53,782 76,720 88,282
-------------------------------------
Cash flows from investing activities:
Change in short-term investments (30,761) (29,519) (83,872)
Purchases of property and equipment (13,444) (20,858) (39,221)
Purchase of technology and related costs -- -- (11,500)
Purchase of long-term investment -- -- (17,500)
Capitalization of software development costs (1,539) (1,000) (1,000)
Purchase of businesses, net of cash acquired (4,512) (6,265) --
-------------------------------------
Net cash used in investing activities (50,256) (57,642) (153,093)
-------------------------------------
Cash flows from financing activities:
Principal payments under capital lease obligations (386) -- --
Principal payments under debt obligations -- -- (5,481)
Proceeds from sale of common stock, net 12,151 19,810 27,974
Purchases of treasury stock -- -- (14,817)
-------------------------------------
Net cash provided by financing activities 11,765 19,810 7,676
-------------------------------------
Effect of exchange rate changes on cash 148 364 (154)
-------------------------------------
Net increase (decrease) in cash and cash equivalents 15,439 39,252 (57,289)
Cash and cash equivalents, beginning of year 36,502 51,941 91,193
-------------------------------------
Cash and cash equivalents, end of year $ 51,941 $ 91,193 $ 33,904
=====================================
Supplemental disclosure of cash flow information:
Cash paid during the year for:
Interest $ -- $ -- $ 685
Income taxes $ 1,218 $ 1,946 $ 16,400
Non-cash transactions:
Purchase of technology for notes $ -- $ -- $ 28,500
</TABLE>
SEE ACCOMPANYING NOTES.
<PAGE> 15
NOTES TO CONSOLIDATED FINANCIAL STATEMENTS
NOTE 1. SUMMARY OF SIGNIFICANT ACCOUNTING POLICIES
FISCAL YEAR END Synopsys, Inc. (Synopsys or the Company), has a fiscal year end
that ends on the Saturday nearest September 30. Fiscal 1994, 1995, and 1996 were
52-week years. For presentation purposes, the consolidated financial statements
and notes refer to the calendar month end.
PRINCIPLES OF CONSOLIDATION The consolidated financial statements include the
accounts of the Company and all of its subsidiaries. All significant
intercompany accounts and transactions have been eliminated.
FOREIGN CURRENCIES The functional currency of Synopsys' foreign subsidiaries is
the local currency. Synopsys translates all assets and liabilities to U.S.
dollars at the current exchange rates as of the applicable balance sheet date.
Revenue and expenses are translated at the average exchange rates prevailing
during the period. Gains and losses resulting from the translation of the
foreign subsidiaries' financial statements are reported as a separate component
of stockholders' equity. The net gains and losses resulting from hedging
intercompany balances were not significant.
REVENUE RECOGNITION Revenue consists of fees for licenses and subscriptions of
the Company's software products, sales of system products, maintenance and
support, customer training, and consulting. License revenue is recognized upon
shipment of products and fulfillment of significant acceptance terms, if any.
When the Company receives advance payment for software products, such payments
are recorded as advances and recognized as revenue when products are actually
shipped. The Company has fulfilled certain orders by shipping the product and
providing a temporary access key for software usage. Revenue is deferred until
the Company provides a production key and collectability is reasonably assured.
Revenue from systems products is recognized upon shipment of products and
fulfillment of significant acceptance terms, if any. Revenue from subscriptions
is deferred and recognized ratably over the term that subscription services are
provided, generally twelve months. Maintenance and support revenue is deferred
and recognized ratably over the term of the maintenance agreement, which is
typically twelve months. Revenue from customer training and consulting is
recognized as the service is performed.
PROPERTY AND EQUIPMENT Property and equipment are recorded at cost. Depreciation
and amortization are provided using the straight-line method over the estimated
useful lives of property and equipment (three to five years) or the term of the
applicable lease. Property and equipment detail is as follows:
<TABLE>
<CAPTION>
SEPTEMBER 30,
-------------------
(IN THOUSANDS) 1995 1996
- -------------------------------------------------------
<S> <C> <C>
Computer and other equipment $ 46,801 $ 72,626
Furniture and fixtures 8,174 10,844
Leasehold improvements 4,518 9,025
-------------------
59,493 92,495
Less accumulated depreciation
and amortization (30,773) (40,958)
-------------------
$ 28,720 $ 51,537
===================
</TABLE>
SOFTWARE DEVELOPMENT COSTS Capitalization of computer software development costs
begins upon the establishment of technological feasibility. Software development
costs capitalized were approximately $1,539,000, $1,000,000, and $1,000,000 in
fiscal 1994, 1995, and 1996, respectively.
Amortization of computer software development costs is computed as the greater
of the ratio of current product revenue to the total of current and anticipated
product revenue or the straight-line method over the software's estimated
economic life of approximately two years. Amortization amounted to approximately
$1,229,000, $879,000, and $1,125,000 in fiscal 1994, 1995, and 1996,
respectively.
STOCK SPLIT On August 14, 1995, the Company announced a two-for-one stock split
of its common stock payable in the form of a stock dividend which was
distributed on September 8, 1995, to holders of record on August 25, 1995. All
share, per share, authorized, common stock, and additional paid-in capital
amounts have been restated for all periods presented to reflect the stock split.
<PAGE> 16
EARNINGS PER SHARE Earnings per share is computed using the weighted average
number of common and dilutive common equivalent shares outstanding during the
period. Dilutive common equivalent shares consist of common stock issuable upon
exercise of stock options and warrants using the treasury stock method.
CASH EQUIVALENTS AND SHORT-TERM INVESTMENTS The Company considers all highly
liquid investments with a maturity of less than three months at the time of
purchase to be cash equivalents. Short-term investments include tax-exempt
municipal securities which have underlying maturities of less than one year or
contain put options that are either supported by a letter of credit from a
top-rated bank or insurance company or are over collateralized for redemption at
par at the reset date. Therefore, the underlying maturity for certain items may
exceed one year. At September 30, 1996, the underlying maturities of the
short-term investments are as follows: $106,837,000 within one year, $2,080,000
within one to five years, $10,015,000 within five to ten years, and $83,731,000
after ten years.
The Company accounts for its investments in accordance with Statement of
Financial Accounting Standards (SFAS) No. 115, "Accounting for Certain
Investments in Debt and Equity Securities." All cash equivalents, short-term
investments, and noncurrent investments have been classified as
available-for-sale securities and consisted of the following:
<TABLE>
<CAPTION>
SEPTEMBER 30, 1995
UNREALIZED UNREALIZED ESTIMATED
(IN THOUSANDS) COST GAINS LOSSES FAIR VALUE
- --------------------------------------------------------------------------------------------
<S> <C> <C> <C> <C>
Classified as current assets:
Tax-exempt com-
mercial paper $ 34,533 $-- $-- $ 34,533
Tax-exempt
municipal
obligations 65,889 -- -- 65,889
Money market
preferred stock 43,384 -- -- 43,384
Municipal
auction rate
preferred stock 9,518 -- -- 9,518
----------------------------------------------------
Total securities $153,324 $-- $-- $153,324
====================================================
</TABLE>
<TABLE>
<CAPTION>
SEPTEMBER 30, 1996
UNREALIZED UNREALIZED ESTIMATED
(IN THOUSANDS) COST GAINS LOSSES FAIR VALUE
- ---------------------------------------------------------------------------------------------------
<S> <C> <C> <C> <C>
Classified as current assets:
Tax-exempt com-
mercial paper $ 6,000 $ -- $-- $ 6,000
Tax-exempt
municipal
obligations 107,712 -- -- 107,712
Money market
preferred stock 77,005 -- -- 77,005
Municipal
auction rate
preferred stock 17,946 -- -- 17,946
--------------------------------------------------------
208,663 -- -- 208,663
Classified as non-current assets:
Equity securities 17,500 12,995 -- 30,495
--------------------------------------------------------
Total securities $226,163 $12,995 $-- $239,158
========================================================
</TABLE>
At September 30, 1995, $34,533,000 and $118,791,000 are classified as cash
equivalents and short-term investments, respectively. At September 30, 1996,
$6,000,000 and $202,663,000 are classified as cash equivalents and short-term
investments, respectively. The adjustment to unrealized holding gains on
available-for-sale securities included as a separate component of stockholders'
equity totaled $8,301,000, net of tax, in 1996. See Note 2 of Notes to
Consolidated Financial Statements. Gains and losses on sales of securities have
not been material.
CONCENTRATION OF CREDIT RISK Financial instruments which potentially subject the
Company to concentrations of credit risk consist principally of cash
equivalents, short and long-term investments, and trade receivables. The Company
invests its excess cash in municipal obligations, commercial paper, and in money
market preferred stock of companies with strong credit ratings. These
investments typically bear minimal risk. This diversification of risk is
consistent with the Company's policy to ensure safety of principal and maintain
liquidity.
The Company sells its products to a large number of customers in diversified
industries, primarily in the United States, Europe, and the Pacific Rim. The
Company performs
<PAGE> 17
ongoing credit evaluations of its customers and generally does not require
collateral. Notes receivable of $2,740,000 have been discounted with a financial
institution, and the Company remains contingently liable for these notes. The
Company maintains reserves for potential credit losses and such losses have been
within management's expectations.
ACCRUED LIABILITIES The Company makes estimates and assumptions that affect the
reported amounts of accrued liabilities. Actual expenses could differ from these
estimates. Accrued liabilities are as follows:
<TABLE>
<CAPTION>
SEPTEMBER 30,
(IN THOUSANDS) 1995 1996
- -------------------------------------------------------
<S> <C> <C>
Payroll and related benefits $ 21,918 $ 33,330
Other accrued liabilities 18,263 25,742
-------------------
$ 40,181 $ 59,072
===================
</TABLE>
INCOME TAXES The Company accounts for income taxes in accordance with SFAS No.
109, "Accounting for Income Taxes," which uses the asset-and-liability method.
Under the asset and liability method, deferred tax assets and liabilities are
recognized for the future tax consequences attributable to differences between
the financial statement carrying amounts of existing assets and liabilities and
their respective tax bases. Deferred tax assets are recognized for deductible
temporary differences, net operating loss carryforwards, and credit
carryforwards if it is more likely than not that the tax benefits will be
realized. To the extent a deferred tax asset cannot be recognized under the
preceding criteria, a valuation allowance must be established.
USE OF ESTIMATES The preparation of financial statements in conformity with
generally accepted accounting principles requires management to make estimates
and assumptions that affect the recorded amounts of assets and liabilities,
disclosure of those assets and liabilities at the date of the financial
statements and the recorded amounts of expenses during the reporting period. A
change in the facts and circumstances surrounding these estimates could result
in a change to the estimates and impact future operating results.
FAIR VALUE OF FINANCIAL INSTRUMENTS The Financial Accounting Standards Board's
SFAS No. 107, "Disclosures About Fair Value of Financial Instruments," defines
the fair value of a financial instrument as the amount at which the instrument
could be exchanged in a current transaction between willing parties. The fair
value of the Company's cash, accounts receivable, accounts payable, long-term
debt and foreign currency contracts, approximates the carrying amount.
NEW ACCOUNTING PRONOUNCEMENTS The Financial Accounting Standards Board recently
adopted SFAS No. 123, "Accounting for Stock-Based Compensation." This statement
establishes financial accounting and reporting standards for stock-based
employee compensation plans, including employee stock purchase plans and stock
option plans. SFAS No. 123 is effective for fiscal years beginning after
December 15, 1995 and provides an alternative to Accounting Principles Board's
Opinion (APB) No. 25, "Accounting for Stock Issued to Employees." Management
plans to continue to account for its employee stock plans under APB No. 25 for
purposes of measurement of compensation expense. Accordingly, adoption of SFAS
No. 123 will not have a material effect on the Company's consolidated results
of operations.
The Financial Accounting Standards Board recently adopted SFAS No. 121,
"Accounting for the Impairment of Long-Lived Assets and for Long-Lived Assets
to be Disposed Of" which is effective for fiscal years beginning after
September 1, 1996. This statement requires long-lived assets to be evaluated
for impairment whenever events or changes in circumstances indicate that the
carrying value of an asset may not be recoverable. The adoption of SFAS No. 121
is not expected to have a material impact on the Company's consolidated results
of operations.
RECLASSIFICATIONS Certain amounts reported in previous years have been
reclassified to conform to the fiscal 1996 presentation.
<PAGE> 18
NOTE 2. PURCHASE OF TECHNOLOGY
AND STRATEGIC INVESTMENTS
On February 1, 1996, the Company and International Business Machines
Corporation (IBM) entered into a six-year Joint Development and License
Agreement Concerning EDA Software and Related Intellectual Property (the
Agreement). Pursuant to the Agreement, the Company acquired certain in-process
research and development technology and a non-exclusive license to sublicense
and to use certain existing IBM electronic design automation (EDA) technology
and the underlying intellectual property, and licensed certain of its
EDA-related intellectual property to IBM. In addition, the Company and IBM are
jointly developing new EDA products in the areas of synthesis, test
methodology, design planning, and static timing sign-off. The Company will have
sole ownership of synthesis products and the exclusive right to market test,
design planning, and static timing products (subject to certain rights of IBM
upon termination of the Agreement). In accordance with the Agreement, the
Company paid IBM $11,000,000 in cash and issued $30,000,000 in notes, which
bear interest at three percent, and are payable to IBM upon the earlier of
achievement of scheduled milestones or at maturity in 2006. The notes were
recorded at fair value of $28,500,000, using a discount rate commensurate with
the risks involved. The Company will also pay royalties on revenues from the
sale of new products developed pursuant to the Agreement. As a result of the
transaction, the Company incurred an in-process research and development charge
of $39,700,000 in the second quarter of fiscal 1996. As of September 30, 1996,
the notes had a balance of $24,470,000, of which $15,970,000 is included in
long-term debt. The carrying amount of the debt, including the long-term
portion, approximates the fair value.
On May 7, 1996, the Company and Cooper and Chyan Technology, Inc. (CCT), a
developer of routing technology for printed circuit boards and integrated
circuits, entered into a strategic relationship. As part of this strategic
relationship, the Company purchased 1,206,542 shares, approximately 9.9 percent
of the outstanding shares of CCT, for $14.50 per share. In accordance with SFAS
No. 115, "Accounting for Certain Investments in Debt and Equity Securities,"
the investment has been classified as "available for sale," and an unrealized
gain of $8,301,000, net of taxes, was recorded as a separate component of
stockholders' equity during fiscal year 1996. CCT and Cadence Design Systems,
Inc. recently announced that they had reached an agreement to merge. The
Company is evaluating the effect of such a merger on its relationship with CCT.
NOTE 3. MERGERS
LOGIC MODELING CORPORATION On February 16, 1994, the Company issued
approximately 5,200,000 shares of its common stock in exchange for all the
outstanding shares of capital stock, vested stock options, and warrants of Logic
Modeling Corporation (LMC), a developer of simulation models and modeling
technologies for the verification of electronic designs. The merger was
accounted for as a pooling of interests and, accordingly, the Company's
consolidated financial statements have been restated for all periods.
In fiscal 1994, in connection with the LMC merger, the Company recorded related
costs of approximately $7,400,000, primarily for transaction costs and
elimination of duplicate facilities and equipment. These estimated costs were
reduced by $900,000 in fiscal 1995.
SILICON ARCHITECTS On May 10, 1995, the Company issued approximately 1,400,000
shares of its common stock in exchange for all the outstanding shares of
capital stock and warrants of Silicon Architects, a developer of design
technology for complex application specific integrated circuits (ASICs) and
application specific standard products (ASSPs). Additionally, options to
acquire shares of Silicon Architects' common stock were exchanged for options
to acquire approximately 148,000 shares of the Company's common stock. The
merger was accounted for as a pooling of interests and, accordingly, the
Company's consolidated financial statements have been restated for all
<PAGE> 19
periods. Total revenue and net income for the individual entities are as
follows:
<TABLE>
<CAPTION>
SILICON
(IN THOUSANDS) SYNOPSYS ARCHITECTS COMBINED
- --------------------------------------------------------------------------------
<S> <C> <C> <C>
Six months ended March 31, 1995:
Total revenue $120,500 $ 3,400 $123,900
Net income (loss) 16,140 (16) 16,124
Year ended September 30, 1994:
Total revenue 196,000 3,200 199,200
Net income (loss) 15,750 (1,545) 14,205
</TABLE>
In connection with this merger, the Company recorded related costs of
approximately $900,000, primarily consisting of contract cancellation charges,
transaction fees, and the elimination of duplicate facilities and equipment.
NOTE 4. ACQUISITIONS
CADIS GmbH AND ARCAD SA On May 31, 1994, the Company acquired all the
outstanding stock of Cadis GmbH (Cadis) for approximately $3,600,000 in cash and
notes. Cadis was a software developer specializing in digital signal processing
design. On September 30, 1994, the Company acquired all the outstanding stock of
Arcad SA (Arcad) for approximately $1,500,000 in cash and notes. Arcad was a
software developer of VHDL models specializing in telecommunications standards.
These acquisitions were accounted for by the purchase method of accounting, and
the results of operations of Cadis and Arcad are included in the Company's
consolidated results of operations since the dates of the acquisitions. The
purchase price, acquisition costs, and net liabilities assumed total $7,300,000,
of which $5,900,000 was allocated to in-process research and development
expense.
ARKOS DESIGN, INC. On June 28, 1995, the Company acquired all the outstanding
securities of ARKOS Design, Inc. (ARKOS) for approximately $9,300,000 in cash
and notes. The notes had a balance of $3,100,000 at September 30, 1996, mature
at various dates through 2005, contain certain provisions that could accelerate
maturity, and are included in current liabilities. The Company recently
introduced a product based on ARKOS technology that supports high-speed
validation of integrated circuits (ICs). The acquisition was accounted for by
the purchase method of accounting, and the results of operations of ARKOS are
included in the Company's consolidated results since the date of the
acquisition. The purchase price, acquisition costs, and net liabilities assumed
total $9,700,000, of which $9,200,000 was allocated to in-process research and
development expense.
NOTE 5. COMMON STOCK
STOCK REPURCHASE PROGRAM In May 1996, the Company announced that its Board of
Directors had authorized the repurchase of up to 2,000,000 shares of its
outstanding common stock in the open market over the next 24 months. During
fiscal 1996, the Company purchased 361,494 shares at an average price of
approximately $41.00 per share. The repurchased shares are available for use
under the Company's employee stock plans and for other corporate purposes. All
shares repurchased during fiscal 1996 were reissued by the end of the year.
STOCK OPTIONS Under the Company's 1992 Stock Option Plan (the Plan) and its
predecessor, the 1988 Restricted Stock Plan, the Board of Directors may grant
options or rights to purchase shares of the Company's stock to eligible
individuals at not less than 100% of the fair market value of those shares on
the grant date. Under both plans, the shares and stock options issued to new
employees typically vest 25% after one year with the remaining shares and
options vesting on a pro rata basis over the following 36 months, and shares and
stock options issued to existing employees typically vest on a pro rata basis
over 48 months or 16 quarters.
<PAGE> 20
In October 1994, the Company adopted the 1994 Non-Employee Directors Stock
Option Plan (the Directors Plan) and reserved 200,000 shares for issuance.
Under the Directors Plan, each non-employee member of the Board of Directors
(the Board) is automatically granted an option to purchase 20,000 shares of the
Company's stock upon initial appointment or election to the Board, and 5,000
shares of the Company's stock upon reelection to the Board at not less than
100% of the fair market value of those shares at the grant date. Stock options
granted upon appointment or election to the Board vest 25% annually. Stock
options granted upon reelection to the Board vest 100% after the fourth year of
continuous service.
Prior to the mergers, Silicon Architects had a stock option plan and LMC had a
separate set of stock option plans. Both the Silicon Architects and LMC plans
were terminated as to future grants upon completion of each of the mergers.
Each outstanding option to acquire Silicon Architects stock was converted to an
option to acquire approximately .18 share of the Company's common stock and
each outstanding option to acquire LMC stock was converted to an option to
acquire approximately .14 share of the Company's common stock, under terms
similar to the terms of the Plan.
The following table summarizes stock option activity for the three years ended
September 30, 1996. Stock option activity in fiscal 1994 includes LMC activity
prior to the merger. Stock option activity in fiscal 1994 and 1995 includes
Silicon Architects' activity prior to the merger.
<TABLE>
<CAPTION>
SHARES OPTIONS OUTSTANDING
AVAILABLE SHARES PRICE PER SHARE
- --------------------------------------------------------------------------------------------------
<S> <C> <C> <C>
Balances at September 30, 1993 918,448 5,530,710 $ .0625 - $24.375
Merger with Silicon Architects 185,498 56,026 $ .0140 - $ .7007
Additional shares authorized 2,544,298 --
Granted (2,520,958) 2,520,958 $ 1.205 - $25.000
Exercised -- (1,738,484) $ .0625 - $22.125
Canceled 382,026 (466,216) $ .1125 - $25.000
---------- ----------
Balances at September 30, 1994 1,509,312 5,902,994 $ .0140 - $25.000
Additional shares authorized 2,083,884 --
Granted (3,448,537) 3,448,537 $ 1.205 - $33.500
Exercised -- (1,645,817) $ .0140 - $29.875
Canceled 479,891 (538,338) $ .0140 - $32.750
---------- ----------
Balances at September 30, 1995 624,550 7,167,376 $ .1125 - $33.500
Additional shares authorized 2,089,937 --
Granted (2,228,133) 2,228,133 $ 29.125 - $47.281
Exercised -- (1,514,864) $ .1125 - $37.000
Canceled 614,791 (631,066) $ 1.205 - $37.000
---------- ----------
Balances at September 30, 1996 1,101,145 7,249,579 $ .1125 - $47.281
---------- ----------
</TABLE>
At September 30, 1996, 2,629,140 options were exercisable at prices ranging from
$.1125 to $44.50 per share.
<PAGE> 21
EMPLOYEE STOCK PURCHASE PLAN In January 1992, the Board of Directors and
stockholders adopted the Employee Stock Purchase Plan, under which a total of
1,750,000 shares have been reserved for issuance as of September 30, 1996. Under
the plan, employees are granted the right to purchase shares of common stock at
a price per share that is 85% of the lesser of: (i) the fair market value of the
shares at the beginning of a rolling two-year offering period, or: (ii) the end
of each semi-annual purchase period. During fiscal 1994, 1995, and 1996, shares
totaling 280,850, 247,356, and 310,689, respectively, were issued under the plan
at average prices of $9.57, $17.22, and $18.84 per share, respectively.
NOTE 6. LINES OF CREDIT AND COMMITMENTS
To facilitate foreign currency forward contracts, the Company has three foreign
exchange lines of credit totaling $169,000,000, which expire in October 1996,
May 1997, and June 1997. The Company enters into forward exchange contracts to
hedge foreign currency denominated intercompany balances. Gains and losses on
contracts to hedge foreign currency commitments are recognized during the
periods in which the related instruments are outstanding. At September 30, 1996,
the Company had outstanding forward contracts in yen and European currencies
totaling approximately $4,078,000. The forward exchange contracts are valued at
prevailing market rates. The net gains and losses resulting from hedging
intercompany balances were not significant.
The Company leases its facilities and certain office equipment under operating
lease agreements. The Company's current corporate facility lease expires in
February 2003 and provides for graduated rental payments. The Company has
entered into an additional corporate facility lease. The facility is under
construction and the lease expires ten years after occupancy. The Company is
amortizing the total rent payments over the lease term on a straight-line basis.
At September 30, 1996 future minimum lease payments under operating leases are:
1997 -- $12,443,000; 1998 -- $14,235,000; 1999 -- $14,112,000; 2000 --
$13,252,000; 2001 -- $12,963,000; and $34,802,000 thereafter. Total rent expense
under operating leases was approximately $9,517,000, $12,490,000, and
$14,441,000 in fiscal 1994, 1995, and 1996, respectively.
NOTE 7. INCOME TAXES
As discussed in Note 1, the Company accounts for income taxes in accordance with
SFAS No. 109.
The Company is entitled to a deduction for federal and state tax purposes with
respect to employees' stock option activity. The net reduction in taxes
otherwise payable arising from that deduction has been credited to additional
paid-in capital.
At September 30, 1996, the Company had net operating loss carryovers in foreign
jurisdictions of approximately $700,000 which are available to offset future
taxable income, if any, in those jurisdictions. For U.S. federal income tax
purposes, the Company had research tax credit carryforwards of approximately
$3,300,000 expiring in fiscal years 2009 through 2011, and alternative minimum
tax credit carryforwards of approximately $400,000, which do not expire. In
addition, the Company had research tax credit carryforwards for state income tax
purposes of approximately $1,200,000, which do not expire.
<PAGE> 22
A net deferred tax asset of $2,625,000 and $9,900,000 is included in prepaid
expenses, deferred taxes, and other at September 30, 1995 and 1996,
respectively. The tax effects of temporary differences and carryforwards which
give rise to significant portions of the deferred tax assets and liabilities are
as follows:
<TABLE>
<CAPTION>
SEPTEMBER 30,
(IN THOUSANDS) 1995 1996
- --------------------------------------------------------------------------------
<S> <C> <C>
Deferred tax assets:
Net operating loss carryovers $ 816 $ 400
Tax credit carryovers 6,788 4,885
Deferred revenue 5,991 10,891
Joint venture and acquisition costs -- 12,985
Reserves and other expenses not
currently deductible 5,616 9,354
Depreciation and amortization 476 --
---------------------------
Total gross deferred tax asset 19,687 38,515
Less valuation allowance (15,896) (23,525)
---------------------------
Deferred tax asset 3,791 14,990
---------------------------
Deferred tax liabilities:
Unrealized foreign exchange gain (708) --
Unrealized gain on securities -- (4,669)
Net capitalized software
development costs (458) (421)
---------------------------
Deferred tax liability (1,166) (5,090)
---------------------------
Net deferred tax asset $ 2,625 $ 9,900
===========================
</TABLE>
The change in the valuation allowance was a net decrease of $4,510,000 during
fiscal 1995 and a net increase of $7,629,000 during fiscal 1996. The valuation
allowance applies primarily to those U.S. federal and state timing items that
are expected to be deductible at a point in the future when taxable income is
uncertain.
Subsequently recognized tax benefits relating to the valuation allowance for
deferred tax assets as of September 30, 1996, will be allocated as follows:
<TABLE>
<CAPTION>
(IN THOUSANDS)
- -------------------------------------------------------
<S> <C>
Income tax benefit $ 5,435
Additional paid-in capital 18,090
--------
$ 23,525
========
</TABLE>
Income before income taxes consisted of:
<TABLE>
<CAPTION>
YEAR ENDED SEPTEMBER 30,
(IN THOUSANDS) 1994 1995 1996
- --------------------------------------------------------------------------------
<S> <C> <C> <C>
United States $22,230 $42,178 $30,831
Foreign 1,424 5,530 5,019
-------------------------------------------
$23,654 $47,708 $35,850
===========================================
</TABLE>
The significant components of the provision for income taxes are as follows:
<TABLE>
<CAPTION>
YEAR ENDED SEPTEMBER 30,
(IN THOUSANDS) 1994 1995 1996
- --------------------------------------------------------------------------------
<S> <C> <C> <C>
Current:
Federal $ 965 $ 3,730 $ 9,907
State 146 1,475 1,415
Foreign 928 2,420 2,662
-----------------------------------------
2,039 7,625 13,984
-----------------------------------------
Deferred:
Federal -- -- (6,650)
State -- -- (950)
Foreign (250) (21) 325
-----------------------------------------
(250) (21) (7,275)
-----------------------------------------
Reduction in goodwill
for the foreign tax
benefit from utilization
of acquired company's
tax attributes 960 1,704 --
Charge equivalent to
the federal and state
tax benefit related
to employee stock
options 6,700 8,100 5,441
-----------------------------------------
7,660 9,804 5,441
-----------------------------------------
Provision for
income taxes $ 9,449 $ 17,408 $ 12,150
=========================================
</TABLE>
<PAGE> 23
The provision for income taxes differs from the amount obtained by applying the
statutory federal income tax rate to income before income taxes as follows:
<TABLE>
<CAPTION>
YEAR ENDED SEPTEMBER 30,
(IN THOUSANDS) 1994 1995 1996
- --------------------------------------------------------------------------------
<S> <C> <C> <C>
Statutory federal tax $ 8,279 $ 16,698 $ 12,548
State tax, net of
federal benefit 524 1,086 1,237
Tax benefit from foreign
sales corporation (452) (971) (1,551)
Tax exempt income (789) (1,849) (2,579)
Research and
development
tax credits (666) (950) (503)
Foreign tax in excess
of U.S. statutory tax 753 370 377
Non-deductible
merger and acquisition
expenses and other 1,800 3,024 2,621
-------------------------------------------
$ 9,449 $ 17,408 $ 12,150
===========================================
</TABLE>
NOTE 8. WORLDWIDE OPERATIONS
The Company operates in a single industry segment, the development, marketing,
and support of electronic design automation software and systems products. The
Company markets its products through several wholly-owned foreign subsidiaries.
The Company's operations by geographic area were as follows:
<TABLE>
<CAPTION>
YEAR ENDED SEPTEMBER 30,
(IN THOUSANDS) 1994 1995 1996
- --------------------------------------------------------------------------------
<S> <C> <C> <C>
Revenue
North America $ 184,977 $ 237,690 $ 325,346
Europe 41,480 52,342 64,805
Pacific Rim 53,010 85,671 108,397
Transfers between
geographic areas (80,267) (110,203) (145,048)
----------------------------------------------
Consolidated $ 199,200 $ 265,500 $ 353,500
----------------------------------------------
Operating income:
North America $ 16,992 $ 20,220 $ 31,653
Europe 7,686 9,606 9,765
Pacific Rim 10,222 22,174 27,182
Corporate and other (13,300) (9,200) (39,700)
----------------------------------------------
Consolidated $ 21,600 $ 42,800 $ 28,900
----------------------------------------------
Identifiable assets:
North America $ 67,841 $ 73,771 $ 138,813
Europe 16,586 20,061 24,216
Pacific Rim 27,193 31,962 27,903
Corporate assets
and eliminations 100,329 171,777 218,035
----------------------------------------------
Consolidated $ 211,949 $ 297,571 $ 408,967
==============================================
</TABLE>
Transfers between geographic areas represent both intercompany product and
service revenue accounted for at prices representative of unaffiliated party
transactions, and export shipments directly to customers. In fiscal 1996,
identifiable assets in the Pacific Rim include $12,788,000 of accounts
receivable from customers located in Japan. Management believes allowances are
adequate to cover any uncollected amounts. Corporate assets consist primarily of
cash and investments. In 1994, 1995, and 1996, no customer accounted for more
than ten percent of revenue.
<PAGE> 1
EXHIBIT 21.1
Synopsys, Inc.
Subsidiaries
Name Jurisdiction of Incorporation
---- -----------------------------
Nihon Synopsys K.K. Japan
Synopsys GmbH Germany
Synopsys Holding Co. U.S.A.
Synopsys (India) Pvte. Ltd. India
Synopsys International, Inc. U.S. Virgin Islands
Synopsys Italia, SRL Italy
Synopsys Korea, Inc. Korea
Synopsys (Northern Europe) Ltd. United Kingdom
Synopsys SARL France
Synopsys Scandinavia AB Sweden
Synopsys Singapore Pte. Ltd. Singapore
Arkos Design, Inc. U.S.A.
Synthesis and Optimisation Systems Ltd. Israel
<PAGE> 1
EXHIBIT 23.1
Consent of Independent Auditors
The Board of Directors
Synopsys, Inc.:
We consent to incorporation by reference in the registration statements (Nos.
33-82804, 33-78560, 33-76206, 33-92144 and 33-04410) on Form S-8 of Synopsys,
Inc. of our reports dated October 18, 1996, relating to the consolidated balance
sheets of Synopsys, Inc. and subsidiaries as of September 30, 1995 and 1996, and
the related consolidated statements of income, stockholders' equity, and cash
flows for each of the years in the three-year period ended September 30, 1996,
and the related schedule, which reports appear or are incorporated by reference
in the September 30, 1996, annual report on Form 10-K of Synopsys, Inc.
KPMG Peat Marwick LLP
Palo Alto, California
December 20, 1996
<TABLE> <S> <C>
<ARTICLE> 5
<CIK> 0000883241
<NAME> SYNOPSYS, INC.
<MULTIPLIER> 1,000
<S> <C>
<PERIOD-TYPE> YEAR
<FISCAL-YEAR-END> SEP-30-1996
<PERIOD-START> OCT-01-1995
<PERIOD-END> SEP-30-1996
<CASH> 33,904
<SECURITIES> 202,663
<RECEIVABLES> 64,746
<ALLOWANCES> 3,661
<INVENTORY> 0
<CURRENT-ASSETS> 317,627
<PP&E> 92,495
<DEPRECIATION> 40,958
<TOTAL-ASSETS> 408,967
<CURRENT-LIABILITIES> 160,250
<BONDS> 15,970
0
0
<COMMON> 404
<OTHER-SE> 232,343
<TOTAL-LIABILITY-AND-EQUITY> 408,967
<SALES> 353,500
<TOTAL-REVENUES> 353,500
<CGS> 38,893
<TOTAL-COSTS> 38,893
<OTHER-EXPENSES> 285,707
<LOSS-PROVISION> 0
<INTEREST-EXPENSE> 1,353
<INCOME-PRETAX> 35,850
<INCOME-TAX> 12,150
<INCOME-CONTINUING> 23,700
<DISCONTINUED> 0
<EXTRAORDINARY> 0
<CHANGES> 0
<NET-INCOME> 23,700
<EPS-PRIMARY> .57
<EPS-DILUTED> .57
</TABLE>
